/FSMGenerator

This is a SystemVerilog (SV) code generator used to create simple Finite State Machines (FSM). You can specify the states, their transition conditions and their outputs and the SV code will be created.

Primary LanguagePython

FSMGenerator

This is a SystemVerilog (SV) code generator used to create simple Finite State Machines (FSM). You can specify the states, their transition conditions and their outputs and the SV code will be created.