/sensix-power-monitor

Sensix PowerMonitor

Primary LanguageC++OtherNOASSERTION

SPD Enclosure based PowerMonitor - 2 DIN Modules - Single/Three Phase

Table of contents

Built with

Software used

Directory structure

  • 3rdparty: Third party code and dependencies
  • cmake: Additional CMake scripts used to configure and build the project
  • data: Resources embedded in the final binary
  • hardware_design: Hardware design files
  • main: ESP IDF component
  • src: Source code
  • src/include: Header files
  • test: Unit tests (meant to be run on PC)

Flash instructions

After setting up the ESP IDF build environment and making sure the tools are available in your PATH, run:

idf.py build # Build the source code
idf.py -p <port> flash
idf.py -p <port> monitor

Running tests

Make sure you have CMake and CTest available in your PATH and a C and C++ compiler available.

Run:

mkdir build && cd build
cmake .. && cmake --build .
ctest

Hardware Design

Design files for PowerMonitor hardware for development:

  • SPD_PowerMonitor-AFE - board containing the analog frontend and isolation barrier
  • SPD_PowerMonitor-Controller - board containing the ESP32 MCU with RS485 and USB for software debugging

Characteristics:

  • Designed to fit into a 2 DIN Module SPD base enclosure
  • Instead of Ethernet and 24V AC power the controller has a USB transciever chip to ease development
  • Powered by USB 5V DC
  • Breakout headers for internal SPI bus in order to experiment with external RAM
  • Breakout headers for I2C bus to add ST NFC module for configuration loading
  • Shunt mounted directly on the SPD spade plugs

Notes

From software side this is the final design, any changes to hardware should be transparent to software. On hardware side, because of chip shortages and especially the low availability of the isolated power supply for the AFE, this design will have to be modified to use other ICs that are available. Analog FE will not change.