LitchiKnight

LitchiKnight's Stars

• microsoft/generative-ai-for-beginners

  18 Lessons, Get Started Building with Generative AI 🔗 https://microsoft.github.io/generative-ai-for-beginners/

  Language:Jupyter Notebook61.6k31.3k

• Anunalla/AHB-MUX-Verif

  UVM verification of manager selection multiplexor of AHB-Lite protocol

  Language:SystemVerilog1

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog920409

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.8k566

• lowRISC/style-guides

  lowRISC Style Guides

  356122

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python996323

• Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step

  This is the main repository for all the examples for the book Practical UVM

  Language:Verilog163106

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.7k565

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k501

• raysalemi/uvmprimer

  Contains the code examples from The UVM Primer Book sorted by chapters.

  Language:SystemVerilog472201

• VerificationExcellence/UVMReference

  Reference examples and short projects using UVM Methodology

  Language:SystemVerilog249150

• nelsoncsc/ISP_UVM

  A Framework for Design and Verification of Image Processing Applications using UVM

  Language:SystemVerilog8738

• marcoz001/axi-uvm

  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

  Language:SystemVerilog10250

• pyuvm/pyuvm

  The UVM written in Python

  Language:Python35769

• openhwgroup/core-v-verif

  Functional verification project for the CORE-V family of RISC-V cores.

  Language:Assembly421218

• openhwgroup/programs

  Documentation for the OpenHW Group's set of CORE-V RISC-V cores

  Language:HTML18696

• fvutils/pyvsc

  Python packages providing a library for Verification Stimulus and Coverage

  Language:Python10925

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  47646

• d2l-ai/d2l-zh

  《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。

  Language:Python61.1k10.8k

• zwdnet/PythonPractice

  极客时间课程《Python核心技术与实战》课程练习实践。

  Language:HTML489249

• LitchiKnight/dsim

  digital verification simulation tool

  Language:Python2

• LitchiKnight/UVM_register_model_best_practice

  1

• hellovimo/uvm_testbench_gen

  Novel GUI Based UVM Testbench Template Builder

  Language:Python11544

• Textualize/rich

  Rich is a Python library for rich text and beautiful formatting in the terminal.

  Language:Python48.8k1.7k

• LitchiKnight/excel2ralf

  Excel file to UVM register model ralf file conversion tool

  Language:Python31

• seabeam/yuu_ahb

  UVM AHB VIP

  Language:SystemVerilog7518

• troyguo/awesome-dv

  Awesome ASIC design verification

  24460

• courageheart/AMBA_APB_SRAM

  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

  Language:SystemVerilog14657

• jessepalomera/10G_EthernetMAC_SystemVerilog_OOP

  Final Project for my course in Advanced Verification with SystemVerilog OOP

  Language:Verilog193

• SWPFlow/C-Project-Based-Tutorials

  A curated list of project-based tutorials in C

  653922