/MIPS_CPU

A naive MIPS simulator for 31 instructions.

Primary LanguageVerilog

MIPS_CPU

For 2020-CS145 course

31 instructions, 5-stage pipeline (Structure)

  • Forwarding & stall
  • predict-not-taken
  • branch prediction

❗ ❗ ❗ Any forms of copying code is strictly prohibited.

Structure of Lab05 (Single cycle)