Lokeshwaran18's Stars
nvdla/sw
NVDLA SW
pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
pulp-platform/riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
ZipCPU/sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
open-sdr/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Jeija/ToA-AoA-Augmented-ChannelCharting
Source Code for Paper "Augmenting Channel Charting with Classical Wireless Source Localization Techniques"
Navigine/Direction-of-Arrival-DoA-Estimation-Algorithm
Project for finding beacon location using Angle of Arrival (AoA) signal. The Direction of Arrival estimation is based on the MUltiple SIgnal Classification (MUSIC) algorithm here.
alexforencich/verilog-axis
Verilog AXI stream components for FPGA implementation
AlexandreRouma/libkcsdr
Control library for the KC908 spectrum analyzer/SDR
emard/wifi_jtag
ESP8266 as wireless JTAG Programmer
emard/ulx3s
PCB for ULX3S FPGA R&D board
WangXuan95/FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器,可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备,只需要3个FPGA普通IO,而不需要额外的接口芯片。
emard/FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器,可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备,只需要3个FPGA普通IO,而不需要额外的接口芯片。
ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD
iamhosseinali/SINE_WAVE_VHDL_GENERATOR
This tool generates a VHDL code for a sine wave generator that can be used in digital signal processing applications.
krakenrf/kfr
Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON)
krakenrf/krakensdr_doa
AngeloJacobo/UberDDR3
Opensource DDR3 Controller
ZipCPU/wb2axip
Bus bridges and other odds and ends
ayushman965/UART_ECHO_STM32_MCU
This is a STM32 Cube IDE non-HAL project. It received data over UART and saves it into the I2C based EEPROM and then read from EEPROM and transmits over UART.
Xilinx/Vitis_Embedded_Platform_Source
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
kunal-kushwaha/DSA-Bootcamp-Java
This repository consists of the code samples, assignments, and notes for the Java data structures & algorithms + interview preparation bootcamp of WeMakeDevs.
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
jotego/jtcores
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
portapack-mayhem/mayhem-firmware
Custom firmware for the HackRF+PortaPack H1/H2
Tooba12322/RTL_Designs
secworks/aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
dreamportdev/Osdev-Notes
A book that explore how to write an Operating System from scratch