LuigiGiuffrida98

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

cv32e40px

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

len5

LEN5 is a coonfigurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Luigi2898

x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

x-heep-docker

This repository contains the dockerfile to build the X-HEEP docker

cosmic-epoch

Next generation Cosmic desktop environment

x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

LuigiGiuffrida98/x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

LuigiGiuffrida98/x-heep-docker

This repository contains the dockerfile to build the X-HEEP docker

LuigiGiuffrida98/llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

LuigiGiuffrida98/core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

LuigiGiuffrida98/len5

LEN5 is a coonfigurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

LuigiGiuffrida98/cv32e40px

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

LuigiGiuffrida98/Luigi2898