Digital VLSI Design RTL to GDS Adam teman
Digital ASIC Design with Verilog - Full CoursePaul franzon
RTL-to-GDSII flow - (Hands-on withEDA Tool)
Digital Electronics and Logic Design Tutorials
Verilog code for 16-bit singlecycle MIPS processor
8bit_MicroComputer_Verilog-master
Detection using Convolutional Neural Network
MathWorks-Machine Learning for Electronic Design Automation, 2018
Dr.Eman related papers . Applications of ML in post silicon verification
. Automatic Generation ofFunctional Coverage Models
. Automatic GenerationofHardwareDesignPropertiesfrom Simulation Traces
. Construction of Coverage Data for PostSilicon Validation Using BigDataTechniques
. Estimation of Formal Verification Cost Using Regression Machine Learning
. Intelligent testbench Automation
. Cross-Product Functional Coverage Analysis Using Machine Learning Clustering Techniques
ML for physical verification paper, 2017
A Hybrid Framework for Functional Verification using RL & DL paper, 2019
Using Machine Learning Techniques for Logic Design Verification paper, 2019
Foster2003_Chapter_FunctionalCoverage book
Machine Learning and Systems for Building the Next Generation of EDA tools, 2018
Optimizing Design Verification using Machine Learning: Doing better than Random, 2019
Path_based_analysis using Mapreduce
Machine_learning_in_VLSI, 2020
Enhancing_the_Performance of FPGA Congestion_Management via Supervised Learning, 2019
Adaptive FPGA Placement Optimization via Reinforcement Learning, 2019
Opportunities of ML in Hardware verification, 2019
Failure Root Cause Analysis Automation on Functional Simulation Regressions, 2019
Support vector machine coverage driven verification for communication cores, old
Functional Test Selection Based on Unsupervised Support Vector Analysis, old