/tyto2

The Tyto Project - version 2

Primary LanguageVHDLGNU Lesser General Public License v3.0LGPL-3.0

The Tyto Project (Version 2)

The Tyto Project is a collection of open source FPGA designs and IP for retro computing and embedded systems, with an emphasis on VHDL and support for both AMD/Xilinx and Intel/Altera targets.

This repository is incomplete. Work to port all the designs and IP from the previous version is ongoing.

A simpler directory structure is used:

  • src contains source code for designs and common IP.

  • build contains makefiles for FPGA builds.

  • test contains makefiles for simulation testbenches.

  • doc contains documentation.

  • submodules contains git submodules.

FPGA Designs

Name Supported Boards Description

ddr3_test

Digilent Nexys Video, QMTech Wukong

A simple DDR3 SDRAM tester based on Joris van Rantwijk’s Pseudo Random Number Generator. Hacks the generated HDL to generate the 200MHz IODELAYCTRL reference clock in the DDR3 IP core MMCM.

hdmi_tpg

Digilent Nexys Video, QMTech Wukong

HDMI test pattern generator. Displays a test pattern on an HDMI monitor at various SD and HD TV resolutions. Includes test audio output.

mb_cb

Digilent Nexys Video, QMTech Wukong

A MicroBlaze CPU with a character buffer display, supporting 480i60 and 576i50 resolutions.

mb_cb_ps2

Digilent Nexys Video

The mb_cb design with an added PS/2 keyboard interface.

mb_fb

Digilent Nexys Video, QMTech Wukong

A MicroBlaze CPU with a 24 bpp high resolution graphics frame buffer held in DDR3 SDRAM, with simple demo application based on Mike Tuupola’s hagl graphics library.

np6532_poc

Digilent Nexys Video, QMTech Wukong, Altera Cyclone V Dev Kit, Terasic DE10-Nano

A proof-of-concept demonstration of the np65 6502 compatible CPU core clocked at 32MHz. Runs Klaus Dormann’s 6502 functional test in a loop.

To build an FPGA design, navigate to the board specific subdirectory under build/ and run the make command.

Simulations

Name Description

np6532_functest

A np65 CPU core running Klaus Dormann’s 6502 functional test.

tb_saa5050

A SAA5050 teletext character generator.

tb_saa5050d

Progressive scan (scan doubling) equivalent of tb_saa5050.

tb_ps2_host

Testbench for PS/2 host IP.

tb_ps2_to_usbhid

Testbench for PS/2 host to USB HID IP.

T65_functest

A T65 6502 compatible core running Klaus Dormann’s 6502 functional test.

Simulations will normally run on any supported simulator (GHDL, NVC, ModelSim/Questa, Vivado). To run a simulation, navigate to its subdirectory under build/ and run the make command.

Dependancies

Note
 ALL designs have submodule dependencies. Please remember to initialise submodules when cloning this repository!

  1. GNU make, GNU core utilities and git are required. These are normally present on Linux systems. Windows users should use MSYS2 to get these tools running - see these notes for further details.

  2. Building an FPGA design requires vendor tools, and produces projects that can be opened and worked on in the vendor’s IDE:

    • For AMD/Xilinx FPGAs, Vivado is required - the free Standard Edition is sufficient. Version since 2020 are supported. Note: designs including a Microblaze soft CPU require Vitis (this includes Vivado). These tools may be obtained from here.

    • For Intel/Altera FPGAs, Quartus Prime is required - the free Lite edition is sufficient. This includes a free edition of the Questa simulator. Versions since 21.1 are supported. Quartus may be obtained from here.

  3. The free open source NVC and GHDL simulators are supported by most simulations. Note that you may need to pre-compile vendor libraries.

  4. Some builds require Python 3.

  5. Projects including a 6502 or compatible CPU require the the ca65 assembler and ld65 linker from the cc65 toolchain.

  6. Visual Studio Code is now a supported make target. Run make vscode to build a directory workspace and open the editor. The build process also generates the required config.v4p file for the excellent VHDL for Professionals (V4P) VS Code extension.

  7. VHDL Style Guide is supported with a custom configuration file. To fix all source files, run make in the src/ directory.

License

This file is part of The Tyto Project. The Tyto Project is free software: you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.

The Tyto Project is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.

You should have received a copy of the GNU Lesser General Public License along with The Tyto Project. If not, see https://www.gnu.org/licenses/.