MPEZZIN

CEAGrenoble - France

Pinned Repositories

cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilog00
IPECC
A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration
Language:VHDL00
openhwgroup_programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Language:HTML00
tristan-unified-access-page
Unified Access Page for the TRISTAN project
Language:HTML00
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Language:HTML20296
core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
Language:SystemVerilog6026

MPEZZIN/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
MPEZZIN/IPECC
A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration
MPEZZIN/openhwgroup_programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Language:JavaScript
MPEZZIN/tristan-unified-access-page
Unified Access Page for the TRISTAN project
Language:HTML