/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

RISC-V Cores and SoC Overview

This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.

Please add to the list and fix inaccuracies.

Cores

Name Supplier Links Priv. spec User spec License
rocket SiFive, UCB Bar GitHub 1.11-draft 2.3-draft BSD
freedom SiFive GitHub 1.11-draft 2.3-draft BSD
Berkeley Out-of-Order Machine (BOOM) Esperanto, UCB Bar GitHub 1.11-draft 2.3-draft BSD
ORCA VectorBlox GitHub RV32IM BSD
RI5CY ETH Zurich, Università di Bologna GitHub RV32IMC Solderpad Hardware License v. 0.51
Zero-riscy ETH Zurich, Università di Bologna GitHub RV32IMC Solderpad Hardware License v. 0.51
Ariane ETH Zurich, Università di Bologna Website,GitHub 1.11-draft RV64GC Solderpad Hardware License v. 0.51
Riscy Processors MIT CSAIL CSG Website,GitHub MIT
RiscyOO MIT CSAIL CSG GitHub 1.10 RV64IMAFD MIT
Minerva LambdaConcept GitHub 1.10 RV32I BSD
OPenV/mriscv OnChipUIS GitHub RV32I(?) MIT
VexRiscv SpinalHDL GitHub RV32I[M][C] MIT
Roa Logic RV12 Roa Logic GitHub 1.9.1 2.1 Non-Commercial License
SCR1 Syntacore GitHub 1.10 2.2, RV32I/E[MC] Solderpad Hardware License v. 0.51
Hummingbird E200 Bob Hu GitHub 1.10 2.2, RV32IMAC Apache 2.0
Shakti IIT Madras Website,GitLab 1.11 2.2, RV64IMAFDC BSD
ReonV Lucas Castro GitHub GPL v3
PicoRV32 Clifford Wolf GitHub RV32I/E[MC] ISC
MR1 Tom Verbeure GitHub RV32I Unlicense
SERV Olof Kindgren GitHub RV32I ISC
SweRV EH1 Western Digital Corporation GitHub RV32IMC Apache 2.0
Reve-R Gavin Stark GitHub 1.10 RV32IMAC Apache 2.0

SoC platforms

Name Supplier Links Core License
Rocket Chip SiFive, UCB BAR GitHub,Simulator Rocket BSD
LowRISC LowRISC CIC GitHub RV32IM BSD
PULPino ETH Zurich, Università di Bologna Website,GitHub RI5CY, Zero-riscy Solderpad Hardware License v. 0.51
PULPissimo ETH Zurich, Università di Bologna Website,GitHub RI5CY, Zero-riscy Solderpad Hardware License v. 0.51
Ariane SoC ETH Zurich, Università di Bologna Website,GitHub Ariane Solderpad Hardware License v. 0.51
OPENPULP ETH Zurich, Università di Bologna Website,GitHub RI5CY, Zero-riscy Solderpad Hardware License v. 0.51
HERO ETH Zurich, Università di Bologna Website,GitHub RI5CY, Zero-riscy Solderpad Hardware License v. 0.51
OpenPiton + Ariane Princeton Parallel Group, ETH Zurich, Università di Bologna Website,GitHub Ariane Solderpad Hardware License v. 0.51, BSD
Briey SpinalHDL GitHub VexRiscv MIT
Riscy AleksandarKostovic GitHub RV64I MIT
Raven RTimothyEdwards, mkkassem (efabless.com) GitHub PicoRV32 ISC
PicoSoC Clifford Wolf GitHub PicoRV32 ISC
Icicle Graham Edgecombe GitHub RV32I ISC

SoCs

Include a chip if it has been fabricated and is either available for sale, available for preorder, or running production workloads internally, and if it has at least one RISC-V hard core (no FPGAs, but non-"SoC" products with controller cores are allowed).

Name Supplier Links Core ISA Devkit Availability
FE310-G000 SiFive Datasheet E31 RV32IMAC HiFive1 public since 2016Q4
FE310-G002 SiFive Product page E31 RV32IMAC HiFive1 Rev B announced 2019Q1, available for preorder
Freedom U540 SiFive Product page U54 (4 cores), E51 (1 management core) RV64GC (application cores), RV64IMAC (management core) HiFive Unleashed development board public since 2018Q1
GAP8 GreenWaves Technologies Product page PULP / 1 + 8 RI5CY RV32IMC (+ Priviledged and custom ISA extensions) GAPuino development board public since 2018Q1
K210 Kendryte Product page, Datasheet, GitHub K210 RV64GC KD233 development board, Sipeed MAIX/M1 development boards public since 2018Q4
RV32M1 NXP Reference Manual and Datasheet RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+ RV32IMC VEGAboard available for preorder as of 2018Q4
RavenRV32 efabless Datasheet, GitHub PicoRV32 RV32IMAC RavenRV32 DevKit Limited Quantity