MarekPikula

FPGA developer by day, DevOps engineer by night.

Samsung ResearchGliwice, Poland

Pinned Repositories

homeassistant-mqtt-filesystem-publisher
Publish file content as MQTT topic compatible with HomeAssistant
Language:Python0 1 00
hugo-profile
A highly customizable and mobile first Hugo template for personal portfolio and blog.
Language:HTML10
PeakRDL-Python-simple
Export Python description from the systemrdl-compiler register model
Language:Python0 3 10
poppler-cpp-doc
Autogenerated cpp reference of poppler
Language:HTML2 2 00
python-headscale-api
Automatically generated Python Headscale API
Language:Python5 1 20
python-poetry-vscode-template
Python + Poetry + VS Code (devcontainer) GitHub template
Language:Python1 1 00
RISC-V-Summit-Europe-ORConf-2024
Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
Language:TeX2 1 00
scalable-pipelined-lookup-fpga
Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path
Language:Scala0 0 00
xournalpp
Notetaking software designed around a tablet. A C++ rewrite of Xournal. Moved from Sourceforge. Check out the glib_new branch if libpoppler>0.16 on your system.
Language:C++5 2 101
PeakRDL-Markdown
Markdown exporter for the PeakRDL toolchain
Language:Python2 3 97

MarekPikula's Repositories

MarekPikula/python-headscale-api
Automatically generated Python Headscale API
Language:Python5 1 20
MarekPikula/RISC-V-Summit-Europe-ORConf-2024
Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
Language:TeX2 1 00
MarekPikula/hugo-profile
A highly customizable and mobile first Hugo template for personal portfolio and blog.
Language:HTML10
MarekPikula/python-poetry-vscode-template
Python + Poetry + VS Code (devcontainer) GitHub template
Language:Python1 1 00
MarekPikula/homeassistant-mqtt-filesystem-publisher
Publish file content as MQTT topic compatible with HomeAssistant
Language:Python0 1 00
MarekPikula/PeakRDL-Python-simple
Export Python description from the systemrdl-compiler register model
Language:Python0 3 10
MarekPikula/scalable-pipelined-lookup-fpga
Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path
Language:Scala0 0 00
MarekPikula/serenitycode.dev
Marek Pikuła – a personal blog
Language:HTML0 2 00
MarekPikula/BlackwireOverview
Blackwire overview, status, roadmap and top-level documentation.
0 0
MarekPikula/BlackwireSpinal
Blackwire SpinalHDL components implementing WireGuard primitives
Language:Scala0 0
MarekPikula/BrightAI-Blackwire
BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
MarekPikula/ChaCha20Poly1305
ChaCha20-Poly1305 AEAD in VHDL
MarekPikula/chaos-assistant
Chaos Assistant TODO app for chaotic project management
Language:Python1 0
MarekPikula/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Language:C
MarekPikula/debian-debootstrap
:earth_africa: `debian-debootstrap` Docker image for multiple architectures
Language:Shell
MarekPikula/Finka
Finka is the VexRiscv based SoC in Blackwire responsible for WireGuard session management
Language:Scala0 0
MarekPikula/FireMarshal
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
MarekPikula/firesim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Language:Scala
MarekPikula/headscale-webui
A simple Headscale web UI for small-scale deployments.
Language:Python0 0
MarekPikula/linux-thead-canmv
Linux kernel source tree for CanMV-K230
Language:C
MarekPikula/meson
The Meson Build System
MarekPikula/pulp-ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
Language:C0 0
MarekPikula/python-betterproto
Clean, modern, Python 3.6+ code generator & library for Protobuf 3 and async gRPC
Language:Python0 0
MarekPikula/riscv-ocelot
Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
Language:Scala0 0
MarekPikula/rvv-bench
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
Language:Assembly
MarekPikula/rvv-bench-results
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
Language:HTML
MarekPikula/SpinalCorundum
SpinalHDL components for Corundum Ethernet
Language:Scala0 0
MarekPikula/SpinalHDL-SystemRDL-demo
Demo of SpinalHDL RegIf to SystemRDL
Language:VHDL1 0
MarekPikula/streamlit
Streamlit — A faster way to build and share data apps.
Language:Python0 0
MarekPikula/SystemRDL-demo
Demo of current SystemRDL export
Language:Python1 0