Pinned Repositories
Phase-Locked-Loop-Design-using-SKY130nm-Technology
Workshop, 31 July 2021 and 1 August 2021
avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
github-markdown-toc
Easy TOC creation for GitHub README.md
RTL-design-with-verilog-using-SKY130-Technology
RTL_Design_and_Synthesis_using_SKY130PDK_Yosys_iVerilog
This github repo is to document the 5day "RTL Design and Synthesis using Verilog and Sky130 library" which was conducted by VLSI System Design Corp.
Sky130-VLSI-Workshop
VSD-IAT repository for workshop
MarichamyDivya's Repositories
MarichamyDivya/Phase-Locked-Loop-Design-using-SKY130nm-Technology
Workshop, 31 July 2021 and 1 August 2021
MarichamyDivya/avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
MarichamyDivya/github-markdown-toc
Easy TOC creation for GitHub README.md
MarichamyDivya/RTL-design-with-verilog-using-SKY130-Technology
MarichamyDivya/RTL_Design_and_Synthesis_using_SKY130PDK_Yosys_iVerilog
This github repo is to document the 5day "RTL Design and Synthesis using Verilog and Sky130 library" which was conducted by VLSI System Design Corp.
MarichamyDivya/Sky130-VLSI-Workshop
VSD-IAT repository for workshop