Mark-RSK/Hastlayer-Hardware-Framework---Xilinx

Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.

Hastlayer Hardware Framework readme

This document is a guideline which provides a brief description of the Hastlayer Hardware Framework for Xilinx FPGAs. The aim of this document is to help the reader to reconstruct and test the Hastlayer FPGA firmware design and to give a hand when you run into a problem.

If you're not familiar with Hastlayer take a look at https://hastlayer.com/.

Table of contents

• Prerequisite requirements
• Getting started
• Running hardware designs
• Version control
• Upgrading the project to the latest Vivado version
• Design reproduction steps
• Testing custom IP cores
• AXI Lite interface slave registers
• Adding custom library functions to the design
• Debugging with an ILA core