Pinned Repositories
aes128-hdl
A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
AMD2901
Conception of AMD2901 processor using VLSI techniques
Cache_CoherenceProtocol
digital-command-control-DCC--on-FPGA
DCC protocol
DihOs_MasshatLinux
Linux-0.11
The old Linux kernel source ver 0.11 which has been tested under modern Linux, Mac OSX and Windows.
MJPEG
Mp-Soc
osvvm_verification
Pibus
Masshat's Repositories
Masshat/AMBA_AXI_AHB_APB
AMBA bus lecture material
Masshat/awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
Masshat/Cores-SweRV
SweRV EH1 core
Masshat/CSE167x
Masshat/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Masshat/dmpvl
Dave McEwan's Personal Verilog Library
Masshat/gdb_systemc_trace
gdb python scripts for SystemC design introspection and tracing
Masshat/gltut
Learning Modern 3D Graphics Programming
Masshat/How-to-Make-a-Computer-Operating-System
How to Make a Computer Operating System in C++
Masshat/kianFpgaPong
Basic Pong you can extend with rotary, sound, vga generator and autopilot
Masshat/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
Masshat/litex
Build your hardware, easily!
Masshat/neorv32
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Masshat/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Masshat/projf-explore
Project F brings FPGAs to life with exciting open-source designs you can build on.
Masshat/PU-RISCV
Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
Masshat/ResuLLMe
Enhance your résumé with Large Language Models
Masshat/RISC-V-project
Description of a RISC-V architecture based on MIPS 3000
Masshat/riscV-1
Open source ISS and logic RISC-V 32 bit project
Masshat/riscv-gcc-prebuilt
Prebuilt rv32i/e RISC-V GCC toolchains for 64-bit x86 Linux.
Masshat/riscv-tests
Masshat/RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
Masshat/riscv_verilator_model
RISCV model for Verilator/FPGA targets
Masshat/SimpleCPU
An open source CPU design and verification platform for academia
Masshat/style-guides
lowRISC Style Guides
Masshat/test-your-sysadmin-skills
:sparkles: A collection of *nix Sysadmin Test Questions and Answers. Test your knowledge and skills in different fields with these Q/A.
Masshat/the-book-of-secret-knowledge
:zap: A collection of awesome lists, manuals, blogs, hacks, one-liners, cli/web tools and more. Especially for System and Network Administrators, DevOps, Pentesters or Security Researchers.
Masshat/tvip-axi
AMBA AXI VIP
Masshat/verilog-axi
Verilog AXI components for FPGA implementation
Masshat/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.