MaxenceBouvier
Research Scientist @ Huawei | PhD, AI Software and AI Hardware Research Scientist | Building AI pipelines that build AI machines
HuaweiSwitzerland
MaxenceBouvier's Stars
NirDiamant/RAG_Techniques
This repository showcases various advanced techniques for Retrieval-Augmented Generation (RAG) systems. RAG systems combine information retrieval with generative models to provide accurate and contextually rich responses.
lsils/mockturtle
C++ logic network library
NVlabs/verilog-eval
Verilog evaluation benchmark for large language model
berkeley-abc/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
lsils/percy
C++ header-only exact synthesis library
SpinalHDL/SpinalHDL
Scala based HDL
teknium1/Prompt-Engineering-Toolkit
whaaswijk/percy
An advanced header-only exact synthesis library
iic-jku/IIC-OSIC-TOOLS
IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
ibm-granite/granite-code-models
Granite Code Models: A Family of Open Foundation Models for Code Intelligence
facebookresearch/chameleon
Repository for Meta Chameleon, a mixed-modal early-fusion foundation model from FAIR.
tulip-control/dd
Binary Decision Diagrams (BDDs) in pure Python and Cython wrappers of CUDD, Sylvan, and BuDDy
ieee-ceda-datc/RDF-2023
NVlabs/CircuitOps
The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
google/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
pulp-platform/bender
A dependency management tool for hardware projects.
pulp-platform/svase
IHP-GmbH/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Thinklab-SJTU/Awesome-LLM4EDA
thedatabusdotio/fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
RayZhhh/funsearch
Implementation for "Mathematical discoveries from program search with large language models".
google-deepmind/funsearch
TabbyML/tabby
Self-hosted AI coding assistant
hkust-zhiyao/RTL-Coder
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
semanser/codel
✨ Fully autonomous AI Agent that can perform complicated tasks and projects using terminal, browser, and editor.
daytonaio/daytona
The Open Source Dev Environment Manager.
astriaai/headshots-starter