A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
Device Support:
- UARTLite
Easy to co-simulate with cemu.
-
Refer to Makefile and modify variables
TOP_NAME
,INC_FILE
,INC_DIR
andINC_PATH
:TOP_NAME
: the name of your CPU top moduleINC_FILE
: all RTL code files included in your designINC_DIR
: home directory of RTL header filesINC_PATH
: cemu core home
-
Makefile targets:
- default: generate executable simulation module
obj_dir/V$(TOP_NAME)
run_func
: run function tests, diff with golden trace intest/func/golden_trace.txt
with AXI latency 34 (read the source code for detail)run_perf
: run all performance tests without diff testdiff_perf
: run all performance tests diff with cemudiff_{bitcount, bubblesort, ..., stringsearch}
: run specified performance test and diff with cemu (suggested)
- default: generate executable simulation module
-
Makefile variables:
T
: dump waveform whenT
is set toy
in repo home directory (note: you'd better dump waveform after the module report Error since the waveform file requires large disk space.)
-
Examples:
- run function tests and dump waveform file:
make run_func T=y
- run crc32 and diff with cemu:
make diff_crc32
- run function tests and dump waveform file: