Michael-J-K94

Pinned Repositories

FFT_reference
FFT_reference code for CA2020 class
Language:Cuda11
6.6.8-pgcxl
Language:C00
LSTM_IOT_SEC
Real-time IOT(ARM) anomaly detection using LSTM accelerator on FPGA/ASIC
Language:VHDL10
mcsim_public_forked
Language:C++00
Michael-J-K94.github.io
My Blog
Language:CSS00
mike_space_saving
Language:Verilog10
public_rfm_verilog
Language:Verilog00
ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Language:C++00
Reconfig_SDFA
Language:Verilog0 0 00
mcsim_public
Language:C++21 0 02

Michael-J-K94's Repositories

Michael-J-K94/LSTM_IOT_SEC
Real-time IOT(ARM) anomaly detection using LSTM accelerator on FPGA/ASIC
Language:VHDL10
Michael-J-K94/mike_space_saving
Language:Verilog10
Michael-J-K94/6.6.8-pgcxl
Language:C00
Michael-J-K94/mcsim_public_forked
Language:C++00
Michael-J-K94/Michael-J-K94.github.io
My Blog
Language:CSS00
Michael-J-K94/public_rfm_verilog
Language:Verilog00
Michael-J-K94/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
Language:C++00
Michael-J-K94/Reconfig_SDFA
Language:Verilog0 0 00