Pinned Repositories
aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Butterfly_Acc
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
DL-on-Silicon
research, experimentation and implementation of hardware-agnostic accelerated DL framework
jmuuu.github.io
myblog
Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
OAFR
PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
PipeCNN_Winograd
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
Miinuuuu's Repositories
Miinuuuu/aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Miinuuuu/Butterfly_Acc
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
Miinuuuu/CHaiDNN
HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs
Miinuuuu/DL-on-Silicon
research, experimentation and implementation of hardware-agnostic accelerated DL framework
Miinuuuu/jmuuu.github.io
myblog
Miinuuuu/Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
Miinuuuu/OAFR
Miinuuuu/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Miinuuuu/PipeCNN_Winograd
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2
Miinuuuu/pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
Miinuuuu/Vitis-Tutorials
Miinuuuu/Vitis_Accel_Examples
Vitis_Accel_Examples
Miinuuuu/32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
Miinuuuu/cores
Various HDL (Verilog) IP Cores
Miinuuuu/DAIN
Depth-Aware Video Frame Interpolation (CVPR 2019)
Miinuuuu/Embedded-Reference-Platforms-User-Guide
Formerly known as the 'reVISION Getting Started Guide', the Embedded Reference Platforms User Guide covers the embedded vision reference platforms for the Vitis environment.
Miinuuuu/explore-virtual-space
Light field-based free-viewpoint VR system
Miinuuuu/ITRI-OpenDLA
OpenDLA for trying the demo and FPGA solution
Miinuuuu/SparseConvNet
Submanifold sparse convolutional networks
Miinuuuu/Static_BFP_HW
This repository contains the hardware implementation for Static BFP convolution on FPGA
Miinuuuu/Super-SloMo
PyTorch implementation of Super SloMo by Jiang et al.
Miinuuuu/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
Miinuuuu/tvip-axi
AMBA AXI VIP
Miinuuuu/unsupervised-video-interpolation
Unsupervised Video Interpolation using Cycle Consistency
Miinuuuu/verilog-axi
Verilog AXI components for FPGA implementation
Miinuuuu/voxel-flow
Video Frame Synthesis using Deep Voxel Flow (ICCV 2017 Oral)
Miinuuuu/vp
Virtual Platform for NVDLA
Miinuuuu/wb2axip
Bus bridges and other odds and ends
Miinuuuu/website
The ZipCPU blog
Miinuuuu/zipcpu
A small, light weight, RISC CPU soft core