MoeFrihat

MoeFrihat's Stars

• cvc5/cvc5

  cvc5 is an open-source automatic theorem prover for Satisfiability Modulo Theories (SMT) problems.

  Language:SMT1.1k237

• dreal/dreal4

  Automated Reasoning in Nonlinear Theories of Reals

  Language:SMT15634

• venkatarun95/ccac

  Automated tool to formally verify congestion control algorithms and find bugs in them

  Language:Python266

• Z3Prover/z3

  The Z3 Theorem Prover

  Language:C++10.5k1.5k

• wesm/pydata-book

  Materials and IPython notebooks for "Python for Data Analysis" by Wes McKinney, published by O'Reilly Media

  Language:Jupyter Notebook22.4k15.3k

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4.1k609

• microsoft/Quantum

  Microsoft Quantum Development Kit Samples

  Language:Jupyter Notebook3.9k923

• krishnakumarsekar/awesome-quantum-machine-learning

  Here you can get all the Quantum Machine learning Basics, Algorithms ,Study Materials ,Projects and the descriptions of the projects around the web

  Language:HTML2.8k677

• Qiskit/qiskit

  Qiskit is an open-source SDK for working with quantum computers at the level of extended quantum circuits, operators, and primitives.

  Language:Python5.5k2.4k

• ultraembedded/cores

  Various HDL (Verilog) IP Cores

  Language:Verilog717215

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog899151

• zssloth/Embedded-Neural-Network

  collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

  556120

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  854206

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.3k238

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.5k193

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.6k463

• trivialmips/nontrivial-mips

  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

  Language:SystemVerilog57799

• WangXuan95/USTC-RVSoC

  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

  Language:SystemVerilog36675

• pulp-platform/axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  Language:SystemVerilog1.2k272

• riscv-boom/riscv-boom

  SonicBOOM: The Berkeley Out-of-Order Machine

  Language:Scala1.8k426

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.2k291

• verilator/verilator

  Verilator open-source SystemVerilog simulator and lint system

  Language:C++2.6k627

• raulbehl/100DaysOfRTL

  100 Days of RTL

  Language:SystemVerilog34399

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.4k217

• steveicarus/iverilog

  Icarus Verilog

  Language:C++2.9k534

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.6k892

• teivah/algodeck

  An Open-Source Collection of Flash Cards to Help You Preparing Your Algorithms & Data Structures and System Design Interviews 💯

  Language:HTML5.7k569

• mandliya/algorithms_and_data_structures

  180+ Algorithm & Data Structure Problems using C++

  Language:C++6k1.3k

• yangshun/tech-interview-handbook

  💯 Curated coding interview preparation materials for busy software engineers

  Language:TypeScript120k14.9k

• bregman-arie/devops-exercises

  Linux, Jenkins, AWS, SRE, Prometheus, Docker, Python, Ansible, Git, Kubernetes, Terraform, OpenStack, SQL, NoSQL, Azure, GCP, DNS, Elastic, Network, Virtualization. DevOps Interview Questions

  Language:Python67.2k15k