MohammadNiknam17/12BIT-Counter-to-7segment-output-VHDL-FPGA
These are VHDL codes for 12Bit counter to 7segment output. contains binary to BCD converter base on double dabble algorithm.
VHDLMIT
These are VHDL codes for 12Bit counter to 7segment output. contains binary to BCD converter base on double dabble algorithm.
VHDLMIT