Pinned Repositories
dvcon_download
Download proccedings from DVCon
English-level-up-tips-for-Chinese
可能是让你受益匪浅的英语进阶指南
motivated_verifier
open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Open_RegModel
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
YASA
:snail:Yet Another Simulation Architecture
MotivatedVerifier's Repositories
MotivatedVerifier/dvcon_download
Download proccedings from DVCon
MotivatedVerifier/English-level-up-tips-for-Chinese
可能是让你受益匪浅的英语进阶指南
MotivatedVerifier/motivated_verifier
MotivatedVerifier/open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
MotivatedVerifier/Open_RegModel
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
MotivatedVerifier/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
MotivatedVerifier/YASA
:snail:Yet Another Simulation Architecture