/verilogModuleAddPrefix

verilog module add prefix script 可用于ysyx项目添加学号

Primary LanguagePythonGNU General Public License v3.0GPL-3.0

verilogModuleAddPrefix

Add prefix to Verilog/SystemVerilog module names and update instances

可用于ysyx项目添加学号

# usage
python3 verilogAutoPrefix.py "$(VERILOG_SRC_DIR)" "$(PREFIX)" "$(IGNORE_NAME)"
# for ysyx project:
python3 verilogAutoPrefix.py "$(VERILOG_SRC_DIR)" "$(STUID)_" "$(STUID)"

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