MrCappuccino

MrCappuccino's Stars

• zhengzhideakang/Verilog--FIFO

  包含同步FIFO，异步FIFO，不同位宽转换

  Language:Verilog5

• Shehab-Naga/ddr5_phy

  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

  Language:SystemVerilog4222

• demonmon/ic

  Language:C1

• KULeuven-MICAS/tinyvers

  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.

  Language:SystemVerilog131

• Verdvana/Async_FIFO

  位宽和深度可定制的异步FIFO

  Language:SystemVerilog127

• peilin-chen/Zhulong-RISCV-CPU

  CPU Design Based on RISCV ISA

  Language:Verilog8220

• sifive/block-nvdla-sifive

  Language:Verilog4227

• aq12138/Git_Bilbili

  verilog

  Language:Verilog214

• zebmehring/Processor-Cache

  A Verilog implementation of a processor cache.

  Language:Verilog236

• Paraoia/CS-Cache

  Design a cache by using Verilog

  Language:Verilog6

• Frightwig/Handshake_protocol_of_AXI4

  handshake protocol with delay

  Language:Verilog7

• RV-BOSC/OpenNoC

  Language:Verilog738

• RookieICer/CompileFileListGrep

  Language:Perl1

• MichaelMelkor/Vivado_Batch_Mode_Tool

  A tool for those who want to use Vivado's batch mode more easily

  Language:Tcl174

• name99-org/AArch64-Explore

  Language:Mathematica25626

• troyguo/awesome-dv

  Awesome ASIC design verification

  27467

• itcharge/LeetCode-Py

  ⛽️「算法通关手册」：超详细的「算法与数据结构」基础讲解教程，从零基础开始学习算法知识，850+ 道「LeetCode 题目」详细解析，200 道「大厂面试热门题目」。

  Language:Python6.2k1.1k

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.2k548

• abdelrhman-oun/DDR5_PHY_WriteOperation

  Language:SystemVerilog3612

• LogicTronix/Vitis-AI-Reference-Tutorials

  Tutorials on Vitis AI Created by LogicTronix!

  Language:Python237

• OSCPU/yosys-sta

  Language:Verilog4710

• Xilinx/libsystemctlm-soc

  SystemC/TLM-2.0 Co-simulation framework

  Language:Verilog22869

• vipinkmenon/fpgadriver

  Language:Verilog73

• opencpi/opencpi

  Open Component Portability Infrastructure

  Language:Verilog5921

• michaelehab/AES-Verilog

  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

  Language:Verilog8520

• holdenQWER/my_vim_config

  Language:Vim script21

• holdenQWER/python_for_IC

  maybe useful python scripts for ICer

  Language:Python74

• holdenQWER/CDC_example

  CDC example code for CSDN blog

  Language:Verilog102

• TinyTapeout/tinytapeout-03

  Language:Verilog146

• Advanced-Microelectronics-Group/OpenC910_Modified

  commit rtl and build cosim env

  Language:SystemVerilog368