Pinned Repositories
2021Q2-hackathon
2021 Q2 全国联动黑客松大赛
_mrwater98.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
backdoors101
cov4rtl
This repo is to investigate aims to study the distribution of different coverage point(e.g., branch, toggle, etc.) under different testing methods (e.g., random, formal).
CPP-GoBang-AI
Fuzz_RTL
hw-cbmc
The HW-CBMC and EBMC Model Checkers for Verilog
ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
vcd2stimuli
yices_example
The purpose of this repository is to provide some references for my use of Yices.
MrWater98's Repositories
MrWater98/cov4rtl
This repo is to investigate aims to study the distribution of different coverage point(e.g., branch, toggle, etc.) under different testing methods (e.g., random, formal).
MrWater98/CPP-GoBang-AI
MrWater98/Fuzz_RTL
MrWater98/hw-cbmc
The HW-CBMC and EBMC Model Checkers for Verilog
MrWater98/ip-cores
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
MrWater98/vcd2stimuli
MrWater98/yices_example
The purpose of this repository is to provide some references for my use of Yices.
MrWater98/2021Q2-hackathon
2021 Q2 全国联动黑客松大赛
MrWater98/_mrwater98.github.io
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
MrWater98/antlr4
ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
MrWater98/avr
Reads a state transition system and performs property checking
MrWater98/Awesome-EDA-Testing-Paper
MrWater98/awesome-hardware-tools
List of awesome open source hardware tools
MrWater98/awesome-symbolic-execution
A curated list of awesome symbolic execution resources including essential research papers, lectures, videos, and tools.
MrWater98/cacti
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
MrWater98/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
MrWater98/env-xs-ov-00-bpu
香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境
MrWater98/FlattenRTL_SV
MrWater98/fuzzing-learning-in-30-days
MrWater98/gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
MrWater98/hdl-benchmarks
Collection of digital hardware modules & projects (benchmarks)
MrWater98/labs-with-cva6
Advanced Architecture Labs with CVA6
MrWater98/motor-federated-backdoor
MrWater98/mrwater98.github.io
MrWater98/pymag-trees
Code from the article "Drawing Good-looking Trees" in Python Magazine
MrWater98/SAFERand
MrWater98/SmartContractCollector
MrWater98/Solar_Steam_Generation
MrWater98/Student-resources
本文介绍的是利用学生、教职工身份可以享受到的相关学生优惠、教育优惠或教师优惠的权益，但也希望各位享受权利的同时不要忘记自己的义务，不要售卖、转手自己的学生优惠、教育优惠的资格，使得其他同学无法受益。
MrWater98/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.