Pinned Repositories
UETRV-PCore
Linux Capable 32-bit RISC-V based SoC in System Verilog
DDV-DBS
The repo is created to manage the progress of all trainees enrolled in Digital Design and Verification Training 2024 at Maktab e Digital Systems (MEDS), UET Lahore under the sponsorship of DreamBig Semiconductors.
DDV-DBS
The repo is created to manage the progress of all trainees enrolled in Digital Design and Verification Training 2024 at Maktab e Digital Systems (MEDS), UET Lahore under the sponsorship of DreamBig Semiconductors.
Design_Verification
Files
Run the bash script file in the repository to install Verilator .
RISCV_Pipelined_Core
RISCV Core supporting RV32I ISA and classical 5 stage pipeline . This core also has a forwarding unit for efficiently handling data hazards .
RISCV_Single_Cycle_Core
Mujtabadar537's Repositories
Mujtabadar537/DDV-DBS
The repo is created to manage the progress of all trainees enrolled in Digital Design and Verification Training 2024 at Maktab e Digital Systems (MEDS), UET Lahore under the sponsorship of DreamBig Semiconductors.
Mujtabadar537/Design_Verification
Mujtabadar537/Files
Run the bash script file in the repository to install Verilator .
Mujtabadar537/RISCV_Pipelined_Core
RISCV Core supporting RV32I ISA and classical 5 stage pipeline . This core also has a forwarding unit for efficiently handling data hazards .
Mujtabadar537/RISCV_Single_Cycle_Core