NAvi349/mixed-riscv-soc

This repository contains the work as part of the 1 day workshop on Mixed-Signal RISC-V based SoC on FPGA sponsored by the OSFPGA Foundation

• Introduction
  • Mixed-Signal Design
  • Verification
• RVMYTH RISC-V Core
• TL - Verilog
  • Timing Abstraction
• ASIC Vs FPGA
• Makerchip
• TLV to RTL
  • Steps to convert TL - Verilog to System Verilog/verilog
• iverilog Simulation
  • Assembly Program in the .tlv file
  • iverilog flow
• FPGA Flow
  • PLL
  • ILA ( Integrated Logic Analyzer )
• RTL Simulation in Vivado
• FPGA Synthesis
• Bit-stream Generation and Program FPGA Step
• Acknowledgements

Introduction

Mixed-Signal Design

• Analog IP and Digital IP on the same package (chip)
• In this workshop, RVMYTH is interfaced with a PLL (avsdpll_1v8)
• PLL acts as a multiplier here

Verification

Verification is done in two parts

• RTL Flow (iverilog and GTKwave)
• FPGA Flow (Xilinx Vivado)

RVMYTH RISC-V Core

• RV32I Instruction Set
• Written in TL - Verilog
• 5 staged Pipelined processor
  • Fetch Stage
  • Decode Stage
  • Execute Stage
  • Memory Access Stage
  • Register Write Back Stage
• Data Hazards solved using Register Bypass (forwarding0 technique
• b - type and j - type instructions have two-cycle latency

TL - Verilog

• Design is done at the Transaction Level MOdelling
• It is an extension of TL-X
• TL - Verilog makes it easier to design complex

Timing Abstraction

|example
  @1
    ---pipeline-stage-1---
  @2
    ---pipeline-stage-2---   
  @3
    ---pipeline-stage-3---

• TL - Verilog makes retiming extremely easy.
• In System Verilog/Verilog when we want to add more pipeline stages, we have to create more flip flops and also duplicate the signal declarations for each pipeline stage
• In TL - Verilog, we just have to move the computation to a different pipeline stage

Example - warp - V core created by Steve Hoover, founder of EDA, is a highly parameterized processor

ASIC Vs FPGA

ASIC	FPGA
Not reconfigurable	Reconfigurable
Final Stage implementation	Useful in prototyping a design
Huge time required to design	Less Time Comparatively

Makerchip

TLV to RTL

• Icarus Verilog - RTL Simulation Tool

• **GTKWave **- waveform viewer

• Vivado HL Design Edition

• SandPiper SaaS - converts to TLV to Verilog/System Verilog

• Installation link - https://pypi.org/project/sandpiper/

Steps to convert TL - Verilog to System Verilog/verilog

i. git clone https://github.com/shivanishah269/risc-v-core.git ii. cd vsdfpga/verilog

We shall now verify the PLL.

iverilog Simulation

Assembly Program in the .tlv file

• This program basically generates a waveform whose values start from 0 to 255 and back again.

iverilog flow

iverilog rvmyth_pll_tb.v rvmyth_pll.v clk_gate.v 
./a.out
gtkwave rvmyth_pll.vcd

• The PLL output becomes the input to the RISC V Core.
• We can also the view the signal in analog format

FPGA Flow

• PPLE is the Xilinx Vivado IP.

PLL

i. Create a new project.

ii. Select the zedboard from the parts list.

iii. Add rvmyth.v, top_SoC.v and clk_gate.v as design sources

iv. Generate PLL and ILA IP from Xilinx Catalog

v. Select PLL and 33 MHz as the input clock

vi. Enable override mode in PLLE2 Tab and compensation as BUF_IN

vii. Click Finish

ILA ( Integrated Logic Analyzer )

• It is used for monitoring internal signals in our design

i. Search ILA in the IP catalogue and select Integrated Logic Analyzer

ii. Set number of probes as 3 and sample depth as 131072

iii. Set probe length as 8 bits

iv. Click Finish

RTL Simulation in Vivado

i. Add top_SoC_tb.v as source.

ii. Run RTL Simulation and run for 50000 units

33 MHz clock is the input 10n MHz clock generated for Core

iii. Also view the DAC signal as analog format

FPGA Synthesis

• Synthesis - mapping the netlist to the standard cell libraries or the actual the gates present in the FPGA
• Constraints file specifies pin mapping for simulation

i. Add constraints file constraints.xdc

ii. Run Synthesis

iii. Now run Implementation

• Optimization
• Placing
• Routing

• It fails to meet timing constraints

• Slack is negative here for hold

• It is actually due to a false path from PLL to ILA.

iv. Solving Timing Issues

• Include these in the constraints.sdc file

set_false_path -hold -from [get_pins uut1/inst/plle2_adv_inst/CLKOUT0] -to [get_pins uut3/inst/ila_core_inst/*D]
set_false_path -hold -from [get_pins uut1/inst/plle2_adv_inst/CLKOUT0] -to [get_pins uut3/inst/ila_core_inst/u_trig/u_trig/U_TM/N_DDR_MODE.G_NMU[2] .U_M/allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/*/D]

v. Implementation Design

Bit-stream Generation and Program FPGA Step

(This shall be done later after I obtain a Zedboard)

Acknowledgements

[1] Kunal Ghosh - Founder, VSD

[2] Shivani Shah - Course Instructor