NJU-CS-SYS/ArchLab2015

Issues

• 为什么数据口和指令口的行为不一样?

  #14 opened 8 years ago by Wonicon
  1

• 将指令译码表格化，生成对应的 Verilog 代码

  #17 opened 9 years ago by Wonicon
  0

• 100MHZ 的 clk_from_ip 也无法满足时序

  #13 opened 9 years ago by Wonicon
  0

• tag_out 实际上都来自第 0 路？

  #12 opened 9 years ago by Wonicon
  1

• 为什么 COUNT_FINISH 是 1？

  #11 opened 9 years ago by Wonicon
  2

• 强烈建议把Archlab下面的文档与代码剥离

  #9 opened 9 years ago by shinezyy
  0

• CU在MEM段是气泡时保存EPC的策略存在问题

  #8 opened 9 years ago by Wonicon
  0

• 中断与气泡

  #4 opened 9 years ago by Wonicon
  1

• Memory Stall 对转发的影响

  #5 opened 9 years ago by Wonicon
  0

• 不正常的循环

  #3 opened 9 years ago by Wonicon
  1