skipping at a compute target?

[pruhnuhv]

I understand the 'action-optimization' of skipping at various levels in the memory hierarchy which enables skipping memory accesses and thereby saves compute cycles. However, what does the 'compute-optimization' target 'skipping' do in hardware? Given that zeros have been accessed from the last level of the hierarchy and are now present at your compute unit (MAC), they should only be gated, not entirely 'skipped.' I can't find documentation for 'compute-optimization' in the sparse optimization docs.
This question is in reference to the Eyeriss-v2 architecture enabling skipping at the MAC in the MICRO '22 paper's artifact (well, table III in the paper suggests that this should've been 'gating' and not 'skipping').