/Cache-Design-VERILOG

design of a memory sub system with cache memory

Primary LanguageVerilog

Cache-Design-VERILOG

design of a memory sub system with cache memory

Specifications

  1. Size - 512kB
  2. Mappping - Direct Mapping
  3. Write Policy - Write Through
  4. Cache Line Size - 8 words
  5. No of Cache Lines - 64
  6. Replacement Algorithm - None

Simulation Results (using Isim simulator)

Read data when data not available in cache - Empty cache line

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Read data when data available in cache

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Read data when data not available in cache - Tag mismatch

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Write data when data not available in cache - Empty cache line

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Write data when data available in cache - Same cache line

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