design of a memory sub system with cache memory
- Size - 512kB
- Mappping - Direct Mapping
- Write Policy - Write Through
- Cache Line Size - 8 words
- No of Cache Lines - 64
- Replacement Algorithm - None
Simulation Results (using Isim simulator)
Read data when data not available in cache - Empty cache line
![image 1](https://github.com/damithkawshan/Cache-Design-VERILOG/raw/master/simulation%20results/data%20not%20in%20cache.png?raw=true)
Read data when data available in cache
![image 2](https://github.com/damithkawshan/Cache-Design-VERILOG/raw/master/simulation%20results/data%20in%20cache.png?raw=true)
Read data when data not available in cache - Tag mismatch
![image 3](https://github.com/damithkawshan/Cache-Design-VERILOG/raw/master/simulation%20results/no_data_valid_line.png?raw=true)
Write data when data not available in cache - Empty cache line
![image 4](https://github.com/damithkawshan/Cache-Design-VERILOG/raw/master/simulation%20results/write_data_not_exist_cline.png?raw=true)
Write data when data available in cache - Same cache line
![image 5](https://github.com/damithkawshan/Cache-Design-VERILOG/raw/master/simulation%20results/write_data_existing_cache_line_same_addr.png?raw=true)