Pipelined MIPS Processor, Completed while an undergrad at U of R, based on given template code. Any use of this code must be cited.
- Draw Diagram of Existing Components
- Update PC
- May not be starting at the right address?
- Calculate Branch & Jump Addresses
- Use them correctly
- Register Writes
- Memory Reads & Writes
- Check and see if stores are done improperly (Hint, they're not...)
- Forwarding/Bypassing Logic
- Basic Implementation
- JALR & JR
- Handle when it is in the writeback stage during decode
- Forward from Writeback to ALU
- Update Diagram to include this
- get a branch near zero in noio
- syscall 4003 results in segfault every time ...
- always get a jump to zero
- Project Report