NickolayTernovoy
PhD student at MIET; RTL design engineer; RISC-V, Posit enthusiast; e-mail: nickolay.tern@gmail.com telegram: https://t.me/cpu_design
Semidynamics
Pinned Repositories
4way-cache
Verilog cache implementation of 4-way FIFO 16k Cache
Altera-Cyclone-IV-board-V3.0
Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board
awesome-canbus
:articulated_lorry: A curated list of awesome CAN bus tools, hardware and resources
awesome-latticeFPGAs
:book: List of FPGA Lattice boards using open tools
awesome-sky130
A curated list of awesome resources for sky130
mdu
M-extension for RISC-V cores.
risc-v_awesome_list
schoolRISCV
CPU microarchitecture, step by step
schoolRISCV_ICache
Академический проект для исследования прироста производительности процессора в зависимости от конфигурации Иерархии Памяти
SimpleCacheController
Advanced Material: Implementing Cache Controllers
NickolayTernovoy's Repositories
NickolayTernovoy/risc-v_awesome_list
NickolayTernovoy/schoolRISCV_ICache
Академический проект для исследования прироста производительности процессора в зависимости от конфигурации Иерархии Памяти
NickolayTernovoy/awesome-sky130
A curated list of awesome resources for sky130
NickolayTernovoy/Altera-Cyclone-IV-board-V3.0
Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board
NickolayTernovoy/awesome-canbus
:articulated_lorry: A curated list of awesome CAN bus tools, hardware and resources
NickolayTernovoy/awesome-latticeFPGAs
:book: List of FPGA Lattice boards using open tools
NickolayTernovoy/DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
NickolayTernovoy/fpga_101
FPGA 101 lessons/labs
NickolayTernovoy/riscv
RISC-V CPU Core (RV32IM)
NickolayTernovoy/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
NickolayTernovoy/mdu
M-extension for RISC-V cores.
NickolayTernovoy/schoolRISCV
CPU microarchitecture, step by step
NickolayTernovoy/SimpleCacheController
Advanced Material: Implementing Cache Controllers
NickolayTernovoy/accel_int4_mm
NickolayTernovoy/basic_verilog
Must-have verilog systemverilog modules
NickolayTernovoy/basics-graphics-music-verilator-cocotb-support
FPGA exercise for beginners
NickolayTernovoy/caravel
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
NickolayTernovoy/chisel_fma
NickolayTernovoy/chiselv
A RISC-V Core (RV32I) written in Chisel HDL
NickolayTernovoy/DCcontroller
Программное управление блоком питания Agilent E3648A. C#
NickolayTernovoy/fpga-webinar-2020
NickolayTernovoy/fpga.play.pub
Low cost open source Lattice iCE40UP5k FPGA board.
NickolayTernovoy/green_v
NickolayTernovoy/green_v_fpu_posit
NickolayTernovoy/hdl
HDL libraries and projects
NickolayTernovoy/int4_mm
https://caravel-user-project.readthedocs.io
NickolayTernovoy/library_ieee_754_hp_arithmetic
Computer Arithmetics: A library of modules for half-precision floating point arithmetic
NickolayTernovoy/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
NickolayTernovoy/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
NickolayTernovoy/spau
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.