Pinned Repositories
Arty-Z7
Board repository for the Arty Z7
automatic-verilog
automatic-verilog based on vimscript
Communication_Design
Digital_Front_End_Verilog
e200_opensource
The Ultra-Low Power RISC Core
IC_Linux_Config
ic
MATLAB
ninghechuan.github.io
Open-FPGA
Devotes to open source FPGA
Silicon_Peasant
NingHeChuan's Repositories
NingHeChuan/Open-FPGA
Devotes to open source FPGA
NingHeChuan/Digital_Front_End_Verilog
NingHeChuan/Communication_Design
NingHeChuan/Silicon_Peasant
NingHeChuan/IC_Linux_Config
ic
NingHeChuan/ninghechuan.github.io
NingHeChuan/Arty-Z7
Board repository for the Arty Z7
NingHeChuan/automatic-verilog
automatic-verilog based on vimscript
NingHeChuan/e200_opensource
The Ultra-Low Power RISC Core
NingHeChuan/MATLAB
NingHeChuan/MyBlog_Pic
NingHeChuan/verilog_emacsauto.vim
verilog filetype plugin to enable emacs verilog-mode autos
NingHeChuan/wavedrom.github.io
Digital timing diagram editor
NingHeChuan/xuanwu9000
design for yourself soc
NingHeChuan/bigwatermelon
合成大西瓜源码,修改版
NingHeChuan/homebrew-install
homebrew安装使用中科大镜像
NingHeChuan/iverilog
Icarus Verilog
NingHeChuan/logoly
A Pornhub Flavour Logo Generator
NingHeChuan/SpinalHDL
SpinalHDL core
NingHeChuan/SpinalWorkshop
Labs to learn SpinalHDL
NingHeChuan/visual_comm
an interactive visualisation of some basic concepts in wireless communication
NingHeChuan/wujian100_open
IC design and development should be faster,simpler and more reliable