The repository has the labs of the MYTH workshop introduced by Steve Hoover the founder of Redwood EDA. The labs are written in TL-Verilog and the simulation is done on Makerchip.
- UPDATE: The Verilog code is added too with simulation done on Modelsim for day3.
- NOTE: All the labs after the third one are applications of the pipelining idea.
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In day4, I have implemented each part of the RISC-V step by step. The last lab was to implement a testbench to test the code.
- NOTE: As the diagram is getting more complicated, I just took screenshot of the part of the diagram that is related to the ALU
