Multicycle-Processor

The single-cycle processor has three primary weaknesses. First, it requires a clock cycle long enough to support the slowest instruction (lw), even though most instructions are faster. Second, it requires three adders (one in the ALU and two for the PC logic); adders are relatively expensive circuits, especially if they must be fast. And third, it has separate instruction and data memories, which may not be realistic. Most computers have a single large memory that holds both instructions and data and that can be read and written. The multicycle processor addresses these weaknesses by breaking an instruction into multiple shorter steps. In each short step, the processor can read or write the memory or register file or use the ALU. Different instructions use different numbers of steps, so simpler instructions can complete faster than more complex ones.

- Datapath block diagram

Screenshot (134)

- Control unit block diagram

Screenshot (136)

- FSM (The main decoder acts as a FSM)

Screenshot (135)

- The simulation was done on Modelsim and here is a screenshot with the output

Screenshot (130)

Reference: David M. Harris, Sarah L. Harris - Digital Design and Computer Architecture