Open Source Chip Project by University (OSCPU)

Let students design their own chips!

Pinned Repositories

chisel-playground
Language:Scala63 6 130
nexus-am
Language:C8 4 16
NutShell
RISC-V SoC designed by students in UCAS
Language:Scala1.4k 46 102247
NutShell-doc
122 8 128
openperf
Language:C11 4 03
yosys-sta
Language:Verilog61 4 1114
ysyx
一生一芯的信息发布和内容网站
Language:HTML128 5 228
ysyx-exam
Language:Shell21 3 06
ysyx-workbench
Language:Shell140 4 2154
ysyxSoC
Language:Verilog80 6 336

Open Source Chip Project by University (OSCPU)'s Repositories

OSCPU/NutShell
RISC-V SoC designed by students in UCAS
Language:Scala1.4k 46 102247
OSCPU/ysyx-workbench
Language:Shell140 4 2154
OSCPU/ysyx
一生一芯的信息发布和内容网站
Language:HTML128 5 228
OSCPU/NutShell-doc
122 8 128
OSCPU/ysyxSoC
Language:Verilog80 6 336
OSCPU/chisel-playground
Language:Scala63 6 130
OSCPU/yosys-sta
Language:Verilog61 4 1114
OSCPU/ysyx-exam
Language:Shell21 3 06
OSCPU/openperf
Language:C11 4 03
OSCPU/nexus-am
Language:C8 4 16
OSCPU/rt-thread
RT-Thread is an open source IoT operating system.
Language:C6 2 07
OSCPU/riscv-linux
RISC-V Linux Port
Language:C4 3 04
OSCPU/riscv-pk
Language:C4 3 09
OSCPU/riscv-rootfs
Language:C2 2 04
OSCPU/FreeRTOS
Language:C1 3 0
OSCPU/nangate45-sim
Language:Verilog1 3 0
OSCPU/riscv-torture
RISC-V Torture Test
Language:Scala1 2 01
OSCPU/vivado-synth
Language:Tcl1 3 01
OSCPU/xv6-riscv
Xv6 for RISC-V
Language:C1 2 01
OSCPU/bug-needle
Language:Python3 01
OSCPU/difftest
Language:C++2 01
OSCPU/essent-demo-am
Language:C++3 0
OSCPU/memtest86plus-am
AM port of Memtest86+
Language:C0 0
OSCPU/ready-to-run
Binary for NutShell test
3 0