OluwoleOyetoke/Verilog_Three_Lane_Junction_Traffic_Control_Simulator

This project holistically shows a case application of Field Programmable Gates Arrays (FPGAs) in the design of a 3-Lane Left-Hand Drive Cross Junction Traffic Control Simulator with Pedestrian Crossing Allowance. As a visual means of verifying the implemented system, a complete graphics driver is developed to show the real-time movement of the cars in response to the traffic controller states in the system. The hardware circuit and graphics operations are modelled on the FPGA using a textural Hardware Description Language (Verilog HDL) on Quartus II Integrated Development Environment (IDE) and ported to the FPGA on an Altera DE1-SoC through the USB Blaster

Verilog