make verilog with huancun.compile Compilation failed
Closed this issue · 4 comments
yuandj commented
make verilog
mkdir -p build
mill -i XiangShan.runMain top.TopMain -td build \
--config DefaultConfig --full-stacktrace --output-file XSTop.v \
--disable-all --remove-assert --infer-rw \
--repl-seq-mem -c:top.TopMain:-o:build/XSTop.v.conf \
--gen-mem-verilog full \
--num-cores 1
[180/243] huancun.compile
[info] compiling 45 Scala sources to /home/pi/XiangShan/out/huancun/compile/dest/classes ...
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:6:8: not found: object freechips
[error] import freechips.rocketchip.diplomacy._
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:7:8: not found: object freechips
[error] import freechips.rocketchip.tilelink._
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:8:8: not found: object freechips
[error] import freechips.rocketchip.util.BundleField
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:15:38: not found: type TLCustomNode
[error] )(implicit valName: ValName) extends TLCustomNode {
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:13:17: not found: type TLMasterPortParameters
[error] clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:13:44: not found: type TLMasterPortParameters
[error] clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:14:18: not found: type TLSlavePortParameters
[error] managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:14:44: not found: type TLSlavePortParameters
[error] managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:15:21: not found: type ValName
[error] )(implicit valName: ValName) extends TLCustomNode {
[error] ^
[error] /home/pi/XiangShan/huancun/src/main/scala/huancun/BankedXbar.scala:22:72: not found: type TLClientPortParameters
[error] override def mapParamsD(n: Int, p: Seq[TLClientPortParameters]): Seq[TLClientPortParameters] = {
[error] ^
[warn] /home/pi/XiangShan/huancun/src/main/scala/huancun/Slice.scala:412:44: non-variable type argument huancun.noninclusive.MSHR in type pattern Seq[huancun.noninclusive.MSHR] (the underlying of Seq[huancun.noninclusive.MSHR]) is unchecked since it is eliminated by erasure
[warn] case (dir: noninclusive.Directory, ms: Seq[noninclusive.MSHR]) =>
[warn] ^
[warn] /home/pi/XiangShan/huancun/src/main/scala/huancun/Slice.scala:427:38: non-variable type argument huancun.inclusive.MSHR in type pattern Seq[huancun.inclusive.MSHR] (the underlying of Seq[huancun.inclusive.MSHR]) is unchecked since it is eliminated by erasure
[warn] case (_: inclusive.Directory, _: Seq[inclusive.MSHR]) =>
[warn] ^
[warn] two warnings found
[error] 460 errors found
1 targets failed
huancun.compile Compilation failed
make: *** [Makefile:48：build/XSTop.v] 错误 1
wakafa1 commented
请在编译之前先 make init，它会把依赖的子模块克隆下来
yuandj commented
请在编译之前先 make init，它会把依赖的子模块克隆下来
是这个问题应该。能否将 github 的子模块也一并镜像一份到 GITEE 上呢？
root@pi-desktop:/home/pi/XiangShan# make clean
make -C ./difftest clean
make[1]: 进入目录“/home/pi/XiangShan/difftest”
rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key /home/pi/XiangShan/build/simv-compile
rm -rf ../build
make[1]: 离开目录“/home/pi/XiangShan/difftest”
rm -rf ./build
root@pi-desktop:/home/pi/XiangShan# make init
git submodule update --init
上面是更新信息，实际上并没有克隆成功。
wakafa1 commented
可以查看 .gitmodules 文件内容，自行克隆相应的子模块并 checkout 到指定的 branch
wakafa1 commented
看起来您已经解决了这一问题，该 issue 将关闭