OpenXiangShan/HuanCun

Issues

• 请教Huancun模块如何与DRAMsim集成并仿真测试

  #162 opened 5 months ago by JimmyWong1998
  0

• 关于TL--CHI协议

  #163 opened 6 months ago by changekkk
  0

• 关于TileLink协议

  #156 opened 7 months ago by changekkk
  6

• 请教关于缓存中T权限的设计

  #152 opened 9 months ago by user-stu-l
  2

• 有关TL-test用于TileLink香山核内核间一致性验证问题

  #157 opened 8 months ago by charles7098
  2

• 请教有关多核原子操作的问题

  #132 opened a year ago by user-stu-l
  1

• 请教一下为什么总线协议从Tilelink转向了CHI？

  #129 opened a year ago by clp510
  1

• 请教关于core_reset的问题

  #128 opened a year ago by user-stu-l
  2

• 请教一下关于接入Non-inclusive HuanCun作为L2 Cache Probe的问题

  #127 opened a year ago by FuWenyi
  4

• 请教一下有关noninclusive 和inclusive的问题

  #124 opened a year ago by user-stu-l
  3

• can i create slavenodes to replace the ram.nodes in the testtop?

  #110 opened a year ago by user-stu-l
  3

• make test error, tried with java 1.8.0_292 and java 11, ubuntu16.04

  #93 opened a year ago by iamdotasb
  6

• rocket-chip submodule使用https进行clone

  #76 opened 3 years ago by cnjsdfcy
  1

• make verilog with huancun.compile Compilation failed

  #44 opened 3 years ago by yuandj
  4

• 请教关于skipProbeN

  #36 opened 3 years ago by daxxyy123
  1