Pinned Repositories
cross_origen
Provides import and export methods from Origen to common formats e.g. IP-XACT
ijtag
Origen interface/driver for the IEEE 1687 (IJTAG) standard
o2
origen
The Origen Semiconductor Developer's Kit core platform
Origen-SDK.github.io
Generated website for http://origen-sdk.org - DO NOT OPEN PRs HERE!!! Please send them to the source instead: https://github.com/Origen-SDK/origen (or the appropriate plugin)
origen_doc_helpers
Helpers for making rich web-based documents
origen_std_lib
A standard test method library for the Advantest V93000 (and hopefully others in future)
origen_stil
An Origen API to consume test IP in STIL format (IEEE 1450)
origen_swd
Origen driver for the Single Wire Debug protocol
origen_testers
Origen drivers/APIs for ATE tester platforms
Origen's Repositories
Origen-SDK/origen
The Origen Semiconductor Developer's Kit core platform
Origen-SDK/origen_std_lib
A standard test method library for the Advantest V93000 (and hopefully others in future)
Origen-SDK/origen_testers
Origen drivers/APIs for ATE tester platforms
Origen-SDK/cross_origen
Provides import and export methods from Origen to common formats e.g. IP-XACT
Origen-SDK/ijtag
Origen interface/driver for the IEEE 1687 (IJTAG) standard
Origen-SDK/o2
Origen-SDK/Origen-SDK.github.io
Generated website for http://origen-sdk.org - DO NOT OPEN PRs HERE!!! Please send them to the source instead: https://github.com/Origen-SDK/origen (or the appropriate plugin)
Origen-SDK/origen_doc_helpers
Helpers for making rich web-based documents
Origen-SDK/origen_stil
An Origen API to consume test IP in STIL format (IEEE 1450)
Origen-SDK/atp
An abstract test program model for Origen
Origen-SDK/origen_app_generators
New Origen application generators/templates, used by the 'origen new' command
Origen-SDK/origen_core_support
A simple/dummy Origen plugin that is used to test the Origen plugin system
Origen-SDK/origen_sim
Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
Origen-SDK/origen_swd
Origen driver for the Single Wire Debug protocol
Origen-SDK/origen_verilog
Verilog parser and generator to interface Origen with the design/verification world
Origen-SDK/bsdl_origen
Origen-SDK/origen_arm_debug
Origen driver for the ARM debug protocol
Origen-SDK/example_rtl
Contains some example RTL code that is used for testing OrigenSim and other plugins
Origen-SDK/origen_arm
Plugin to Origen to model and drive ARM (https://www.arm.com/) cores.
Origen-SDK/origen_debuggers
Origen-SDK/origen_jtag
JTAG driver for the Origen SDK
Origen-SDK/origen_memory_image
Provides a standard API for consuming memory image files in any format e.g. s-record, hex
Origen-SDK/origen_nexus
Origen driver for the Nexus (IEEE-STO 5001-2003) protocol
Origen-SDK/origen_perforce
Origen revision control driver for Perforce
Origen-SDK/origen_spi
Origen driver to implement SPI
Origen-SDK/origen_standard_subblocks
Simple, elementary, pre-defined subblocks to easily model common SoC blocks.
Origen-SDK/origen_usb_host
Origen USB HOST driver for use in data download to DUT
Origen-SDK/OrigenLink
Origen drivers/APIs for UDOO Board
Origen-SDK/ruby-iar
Ruby-based driver for the IAR toolchain.
Origen-SDK/test_ids
Origen plugin to assign and track test program bin and test numbers