Low Noise Differential Amplifier with JFET Input
This project is inspired by the Stanford Research SR560 Low Noise Voltage Preamplifier, featured in "The Art of Electronics" by Horowitz & Hill (somewhat of a must-have for analog engineers and voltnuts). For explanations refer to said book, an LTSPICE simulation file of the basic topology will also be included here at some point. The schematics of the SR560 can be found here: https://www.physics.wisc.edu/courses/home/spring2020/407/407_Lab_Instrument_Manuals/SR560-low-noise_amplifier-filter/SR560_w_schematics.pdf
It features an improved implementation of the base topology with significantly lower noise, lower BOM cost and reduced footprint, made possible by the extensive use of SMD technology. After SMD assembly the entire board should be cleaned from any flux residue before mounting of the electromechanical components such as relays and trim-potentiometers. An effort was made to use only components that can be hand-soldered without hot air.
To achieve optimum noise performance, careful component selection is required. Once the overall topology and the component values are optimised for noise performance, it comes down to choosing active and passive components that contribute a
Compatible with either Texas Instruments JFE2140 or Linear Systems LSK389/489 as input JFET.
In the direct signal path, the original SR560 uses OP37 and LT1028, which are still very good choices. Both of them are decompensated (as in not unity-gain stable), low-noise, high-precision amplifiers. Substituting them without compromising performance or even improving performance figures is non-trivial. Using unity-gain-stable alternatives like Texas Instruments OPAx211 is possible. OPA2211 is a dual OpAmp and will enable a smaller occupied board area.
All resistors in the direct signal path should be thin/metal-film types with low temperature coefficient and tight tolerances. For the drain resistors and the upper two source resistors, ≤25ppm/K and 0.1% tolerance is strongly recommended. Elsewhere, 50ppm/K and 1% Tolerance is acceptable.
However, even precision resistors aren't made equal. Without going into detail, maximum miniaturisation is not feasible for ultralow noise applications. There are plenty of papers on resistor noise, one of them compares the (excess) current noise of various types: https://dcc.ligo.org/public/0002/T0900200/001/current_noise.pdf
Figures 6 and 10 indicate that among others, Vishay Beyschlag MMA0204 show relatively low excess noise. They are also reasonably priced, widely available and easy to solder by hand. MELF resistors may be seen by some as a weird choice in modern electronics, but Vishay MELFs are without a doubt excellent resistors and fit perfectly on most 1206 footprints.
In the signal chain, either NP0/C0G ceramic or film capacitors (PP/PS) are used. For power filtering, a combination of X7R/X5R ceramics and electrolytic capactitors is employed. The usual rules about capacitor derating apply, maximum miniaturisation is again not feasible.
The smallest widely available latching relays are TE Connectivity Axicom IM and Omron G6K. I prefer made in EU components if possible, so in this case Axicom IM. While the footprints are compatible, attention must be paid to selecting the correct part number and adjusting for the difference in coil resistance.
As far as miniature trim potentiometers go, Bourns 3224W are an obvious choice and widely available in common values.
Ultrasonic cleaning of these components is NOT RECOMMENDED.
First (home-etched) Prototype with through hole components, single layer layout and accordingly high sensitivity to EMI:
First SMD Implementation with some minor layout errors (2-Layer PCB):
This version features full gain switching via relay and CMOS switches, controlled over logic level inputs on the headers.
This version is fully DC-coupled, but AC-coupling capacitors and relays can be added externally.
V2 - work in progress
The original SR560 design with LSK389B and the simulated input referred noise and gain.
Simply reducing the values of the feedback and source resistors by roughly 50% (as suggested in "The Art of Electronics") results in a noticeable improvement, lowering the flatband noise to 2nV/rtHz.
The next step is to adjust the drain resistors and the biasing of the JFET to optimize for noise performance without impacting stability.