Pinned Repositories
GENUVM
Automated script to generate a generic UVM testbench with compatible makefile and internal scripts.
ip_amba_ahb_ms_rtl_v
RTL design for the AMBA AHB protocol.
ip_amba_apb_ms_rtl_v
The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
ip_generic_custom_lfsr_generator_verilog
Custom polynomial ( variable width ) LFSR ( Galios/Fib ) generator
ip_parallel_custom_crc_gerator_verilog
Verilog parallel CRC generation module with custom polynomial and variable width
ip_vga_ctlr_v
VGA controller RTL ( soft ip ) in Verilog
prune_uvmg
GUI based UVM Test Environment generation tool
rtl_template_gen
Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )
rv_namec
RISC-V ( 32b / Single Cycle ) - "RV32I"
std_module
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
PXVI's Repositories
PXVI/ip_amba_apb_ms_rtl_v
The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
PXVI/prune_uvmg
GUI based UVM Test Environment generation tool
PXVI/ip_amba_ahb_ms_rtl_v
RTL design for the AMBA AHB protocol.
PXVI/ip_parallel_custom_crc_gerator_verilog
Verilog parallel CRC generation module with custom polynomial and variable width
PXVI/std_module
All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.
PXVI/GENUVM
Automated script to generate a generic UVM testbench with compatible makefile and internal scripts.
PXVI/ip_vga_ctlr_v
VGA controller RTL ( soft ip ) in Verilog
PXVI/mips-pro-adam
It's a simple verilog based MIPS microarchitecture hardware design.
PXVI/rtl_template_gen
Script to generate a verilog IP template for quick build ( supports makefile, compilefileist and more )
PXVI/rv_namec
RISC-V ( 32b / Single Cycle ) - "RV32I"
PXVI/ip_generic_custom_lfsr_generator_verilog
Custom polynomial ( variable width ) LFSR ( Galios/Fib ) generator
PXVI/ip_serial_custom_crc_gerator_verilog
Verilog serial CRC generation module with custom polynomial and variable width
PXVI/common_scripts
Linux Scripts & Settings ( tcshrc and vim )
PXVI/git_practice
Dummy repo to practice git commands