Pinned Repositories
CellDesign
Adding a Customized Standard Cell into the OpenLane Flow
NASSCOM_SoC_Design
Complete RTL to GDSII flow of a picorv32a core
PLL_130nm
Python_Programs
Learning Python
RISC-V_Core_Myth
riscv-myth-workshop-sep23-Pa1mantri created by GitHub Classroom
RISC-V_HDP
Design of a Customizable RISC-V SoC for Clapswitch Application
TCL_Workshop
5-Day TCL begginer to advanced workshop by VSD
tt07_cdc_fifo
"Clock Domain Crossing FIFO" Tapedout using TInytapeout(tt07) shuttle
VSD_Hardware_Design
Pre and Post Synthesis Simulation of a Design VSDMemSOC
VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
Pa1mantri's Repositories
Pa1mantri/tt07_cdc_fifo
"Clock Domain Crossing FIFO" Tapedout using TInytapeout(tt07) shuttle
Pa1mantri/VSD_Hardware_Design
Pre and Post Synthesis Simulation of a Design VSDMemSOC
Pa1mantri/CellDesign
Adding a Customized Standard Cell into the OpenLane Flow
Pa1mantri/RISC-V_HDP
Design of a Customizable RISC-V SoC for Clapswitch Application
Pa1mantri/VSDMemSOC
VSDMemSOC Implementation flow:: RTL2GDSII
Pa1mantri/NASSCOM_SoC_Design
Complete RTL to GDSII flow of a picorv32a core
Pa1mantri/PLL_130nm
Pa1mantri/Python_Programs
Learning Python
Pa1mantri/RISC-V_Core_Myth
riscv-myth-workshop-sep23-Pa1mantri created by GitHub Classroom
Pa1mantri/TCL_Workshop
5-Day TCL begginer to advanced workshop by VSD
Pa1mantri/VSD_MEMSOC
Caravel intergration of VSDMEMSOC design