This course helps the learners to get familiarized with
(i) Digital Logic Design through the implementation of Logic Circuits using ICs of basic logic gates & flipflops and
(ii) Hardware Description Language based Digital Design. This course helps the learners to design and implement hardware systems in areas such as games, music, digital filters, wireless communications and graphical displays.
Prerequisite : Topics covered under the course Logic System Design (CST 203)
Conduct a minimum of 8 experiments from Part A and a minimum of 4 experiments from Part B. The starred experiments in Part A are mandatory. The lab work should be conducted in groups (maximum group size being 4). The performance of a student in the group should be assessed based on teamwork, integrity and cooperation.
Part A (Any 8 Experiments)
• A 2 hour session should be spent to make the students comfortable with the use of trainer kit/breadboard and ICs.
• The following experiments can be conducted on breadboard or trainer kits.
• Out of the 15 experiments listed below, a minimum of 8 experiments should be
completed by a student, including the mandatory experiments (5).
- Realization of functions using basic and universal gates (SOP and POS forms).
- Design and realization of half adder, full adder, half subtractor and full subtractor using:
a) basic gates (b) universal gates. * - Code converters: Design and implement BCD to Excess 3 and Binary to Gray code
converters.
- Design and implement 4 bit adder/subtractor circuit and BCD adder using IC7483.
- Implementation of Flip Flops: SR, D, T, JK and Master Slave JK Flip Flops using basic
gates.*
- Asynchronous Counter: Design and implement 3 bit up/down counter.
- Asynchronous Counter: Realization of Mod N counters (At least one up counter and one
down counter to be implemented). *
- Synchronous Counter: Realization of 4-bit up/down counter.
- Synchronous Counter: Realization of Mod-N counters and sequence generators. (At least
one mod N counter and one sequence generator to be implemented) *
- Realization of Shift Register (Serial input left/right shift register), Ring counter and
Johnson Counter using flipflops. *
- Realization of counters using IC’s (7490, 7492, 7493).
- Design and implement BCD to Seven Segment Decoder.
- Realization of Multiplexers and De-multiplexers using gates.
- Realization of combinational circuits using MUX & DEMUX ICs (74150, 74154).
- To design and set up a 2-bit magnitude comparator using basic gates.
PART B (Any 4 Experiments)
• The following experiments aim at training the students in digital circuit design with
Verilog. The experiments will lay a foundation for digital design with Hardware
Description Languages.
• A 3 hour introductory session shall be spent to make the students aware of the
fundamentals of development using Verilog
• Out of the 8 experiments listed below, a minimum of 4 experiments should be
completed by a student
Experiment 1. Realization of Logic Gates and Familiarization of Verilog
(a) Familiarization of the basic syntax of Verilog
(b) Development of Verilog modules for basic gates and to verify truth tables.
(c) Design and simulate the HDL code to realize three and four variable Boolean
functions
Experiment 2: Half adder and full adder
(a) Development of Verilog modules for half adder in 3 modeling styles (dataflow/
structural/behavioural).
(b) Development of Verilog modules for full adder in structural modeling using half
adder.
Experiment 3: Design of code converters
Design and simulate the HDL code for
(a) 4- bit binary to gray code converter
(b) 4- bit gray to binary code converter
Experiment 4: Mux and Demux in Verilog
(a) Development of Verilog modules for a 4x1 MUX.
(b) Development of Verilog modules for a 1x4 DEMUX.
Experiment 5: Adder/Subtractor
(a) Write the Verilog modules for a 4-bit adder/subtractor
(b) Development of Verilog modules for a BCD adder
Experiment 6: Magnitude Comparator
Development of Verilog modules for a 4 bit magnitude comparator
Experiment 7: Flipflops and shiftregisters
(a) Development of Verilog modules for SR, JK, T and D flip flops.
(b) Development of Verilog modules for a Johnson/Ring counter
Experiment 8: Counters
(a) Development of Verilog modules for an asynchronous decade counter.
(b) Development of Verilog modules for a 3 bit synchronous up-down counter