PebPeb

BEAN-1

Binary Execution and Analysis Node

BEAN-2

From the creator of the BEAN-1 comes the BEAN-2....

Compiler-RV32I

Rudimentary compiler for bare bones RV32I on my custom Single Cycle CPU

GPIO_Example_2

I-Spend-To-Much-Time-On-My-Phone

my-website

RISC-V-Programs

RISC-V Programs is a collection of programs writen in C and Assembly for various RISC-V implementations.

Single-Cycle-RV32I

Single Cycle CPU using the RV32I Base Instruction set

verilog-modules

Archive of all the different general purpose verilog modules that I build

VeroMake

VeroMake is a build kit for making starting and compiling Verilog related projects easier with opensource tools

PebPeb/Single-Cycle-RV32I

Single Cycle CPU using the RV32I Base Instruction set

PebPeb/BEAN-2

From the creator of the BEAN-1 comes the BEAN-2....

PebPeb/BEAN-1

Binary Execution and Analysis Node

PebPeb/Compiler-RV32I

Rudimentary compiler for bare bones RV32I on my custom Single Cycle CPU

PebPeb/I-Spend-To-Much-Time-On-My-Phone

PebPeb/RISC-V-Programs

RISC-V Programs is a collection of programs writen in C and Assembly for various RISC-V implementations.

PebPeb/verilog-modules

Archive of all the different general purpose verilog modules that I build

PebPeb/GPIO_Example_2

PebPeb/my-website

PebPeb/notes

PebPeb/SAP-1

The Simple-As-Possible (SAP) computer is a computer architecture designed for a beginner. The main purpose of this architecture is to introduce the crucial ideas behind computer operation. This project is a rendition of the architecture described in Digital Computer Electronics by Albert Paul Malvino and Jerald A. Brown.

PebPeb/web-content

This repo is just a set of raw files for all related posts and projects on my website

PebPeb/wireguard-manger

To help manage local wireguard VPN peers