RISC-V-PROJECT-ANDESIGHT
Made by Darshil Modha, Tithi Shah and Piyush Saini
A term project about exploration of RISC-V based cores/processors and demonstration of a fundamental software-oriented case study with the help of AndeSight IDE. RISC V is one of the most recent area of research and development in regards to an ISA. As it is open source, it has become very popular among students and industries alike to develop various applications. RISC V has potential to revolutionize the SoC industry as it has better efficiency in terms of power consumption and chip die area as compared to existing ISAs. Our project aims to provide a basic framework and acts as a stepping stone for beginners who want to work with RISC V based processor. This project gives an insight on how to use and write basic program for the peripherals like GPIO, UART and PIT available in the simulator. It also familiarizes any beginner with Eclipse based simulators that are used to program RISC V based processors.
Firstly, we went through the RISC V ISA documentation to acquaint ourselves with the architecture. Next step was to find an environment that could simulate the RISC V based processors for which we chose AndeSightTM (an eclipse-based IDE) because of its satisfactory documentation and responsive technical support team. The team provided us with the processor (NX25F) specific documentation through which we gained knowledge of all peripherals supported on the device. In order to program the peripherals, we looked through the available configuration and header files for the processor. We wrote some basic programs with a few modifications that are presented throughout the report albeit with some simulator specific limitations.
With RISC V being in its early stages of development, the associated IDEs do not provide as many features as their competitive counterparts. Due to this the novice developers are unable to unlock the full potential of the architecture. Nevertheless, the IDE supports basic functionalities that allows the developers to get a gist of the architecture. RISC V has a promising future because of high accessibility, flexibility, and power & area efficiency but has a long way to go before it can compete with the likes of x86, ARM architectures.