Pinned Repositories
5g-ldpc
5g ldpc codes
5G-LDPC-MexFunction
5G LDPC simulation based on MEX function.
Design-and-Verification-of-LDPC-Decoder
- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.
ldpc-3gpp-matlab
Matlab simulations of the encoder and decoder for the New Radio LDPC code from 3GPP Release 15
Prisonercell's Repositories
Prisonercell/5g-ldpc
5g ldpc codes
Prisonercell/ldpc-3gpp-matlab
Matlab simulations of the encoder and decoder for the New Radio LDPC code from 3GPP Release 15
Prisonercell/5G-LDPC-MexFunction
5G LDPC simulation based on MEX function.
Prisonercell/Design-and-Verification-of-LDPC-Decoder
- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.