Pinned Repositories
BitsAndBytes-C-program-CompArch
A comprehensive systems programming toolkit implementing low-level concepts in C, from memory management to OS internals. Features practical implementations of computer architecture concepts with a focus on performance and hardware interaction.
black-parrot
A Linux-capable RISC-V multicore for and by the world
Cache-Coherency-protocols
Implementation of MI, MSI, MESI, MOSI, MOESI, MOESIF protocols in Cache Coherence
Caltech10-CPU
8-bit Harvard Architecture CPU implemented in ABEL
ChampSim-Branch-Predictor-simulator
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
commercial_thermal_map_dataset
dl_accelerator
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
gem5-tutorial-codespace
labs-with-cva6
Advanced Architecture Labs with CVA6
priyanshu.github.io
Personal website
Priyanshumishra77's Repositories
Priyanshumishra77/priyanshu.github.io
Personal website
Priyanshumishra77/ChampSim-Branch-Predictor-simulator
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
Priyanshumishra77/Priyanshumishra77
Priyanshumishra77/3-Wide-RISC-V-OOO-RV32-IM-Processor
3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
Priyanshumishra77/Arm-Helium-Technology
A reference book on M-Profile Vector Extensions (MVE) for Arm Cortex-M Processors
Priyanshumishra77/awesome-leetcode-resources
Awesome LeetCode resources to learn Data Structures and Algorithms and prepare for Coding Interviews.
Priyanshumishra77/binutils-my66000
A port of binutils for Mitch Alsup's My 66000
Priyanshumishra77/cache_simulator
A comprehensive C++20 cache simulator for analyzing memory hierarchy performance with configurable cache levels, replacement policies, and inclusion strategies
Priyanshumishra77/CMSIS-NN
CMSIS-NN Library
Priyanshumishra77/Comp_Arch-Resources
Priyanshumishra77/CUDA-GPU-BOOK-SOLUTION
Complete solutions to the Programming Massively Parallel Processors Edition 4
Priyanshumishra77/dummy32
A 5-stage pipelined, rv32i core with branch prediction and hazard detection
Priyanshumishra77/egos-2000
Envision a future where every student can read all the code of a teaching operating system.
Priyanshumishra77/eGPU
Extending eBPF Programmability and Observability to GPUs
Priyanshumishra77/freess
RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm
Priyanshumishra77/GEM5--OpenXiangShan
Priyanshumishra77/google-benchmark
A microbenchmark support library
Priyanshumishra77/greyhound-ihp
Greyhound on IHP SG13G2 0.13 μm BiCMOS process
Priyanshumishra77/librelane
ASIC implementation flow infrastructure
Priyanshumishra77/magic-trace
magic-trace collects and displays high-resolution traces of what a process is doing
Priyanshumishra77/open-webui
User-friendly AI Interface (Supports Ollama, OpenAI API, ...)
Priyanshumishra77/RISC-32bit-Processor
Priyanshumishra77/riscv-cpu-from-scratch
Priyanshumishra77/RISCV-Scalable-Simulation-tutorial
Priyanshumishra77/rvpu-risc-v-processor
Priyanshumishra77/spring2025-lectures
Language modelling from scratch
Priyanshumishra77/systemverilog-homework
SystemVerilog language-oriented exercises
Priyanshumishra77/tiny-tpu
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
Priyanshumishra77/XiangShan-high-performance-risc-v-processor
Open-source high-performance RISC-V processor
Priyanshumishra77/xs-env
XiangShan Frontend Develop Environment