Errors when compiling verilog modules using verilator

[zhxj9823]

When compiling verilog modules using verilator, the following errors occurred:

%Warning-PINMISSING: verilog/mycpu_top.v:7316:15: Cell has missing pin: 'clk'
7316 | AXI_complex axi3x1 (
| ^~~~~~
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: verilog/mycpu_top.v:7316:15: Cell has missing pin: 'rst'
7316 | AXI_complex axi3x1 (
| ^~~~~~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:325:96: Operator COND expects 2 bits on the Conditional True, but Conditional True's REPLICATE generates 1 bits.
: ... In instance mycpu_top.axi3x1
325 | queuehit_d_rd_id[AXI_RQUEUE_SIZE_B-1:0] = (queuehit_d_rd == {AXI_RQUEUE_SIZE{1'b0}}) ? {AXI_RQUEUE_SIZE_B-1{1'b0}} : queuehit_d_rd_enc + axi_rdqueue_start;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:345:61: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CLOG2 generates 32 bits.
: ... In instance mycpu_top.axi3x1
345 | axi_rd_reg_size [axi_rdqueue_start] <= $clog2(PORT_INST_WIDTH / 8);
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:365:61: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CLOG2 generates 32 bits.
: ... In instance mycpu_top.axi3x1
365 | axi_rd_reg_size [axi_rdqueue_start] <= $clog2(PORT_INST_WIDTH / 8);
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:383:69: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS's REPLICATE generates 96 bits.
: ... In instance mycpu_top.axi3x1
383 | axi_rd_reg_data_out [rid[AXI_RQUEUE_SIZE_B-1:0]] <= {axi_rd_reg_data_out [rid[AXI_RQUEUE_SIZE_B-1:0]] << AXI_R_BUS_WIDTH, rdata};
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:411:33: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's REPLICATE generates 4 bits.
: ... In instance mycpu_top.axi3x1
411 | axi_wr_reg_idlim <= {AXI_R_ID_WIDTH{1'b0}};
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:479:63: Operator GT expects 32 bits on the LHS, but LHS's ARRAYSEL generates 3 bits.
: ... In instance mycpu_top.axi3x1
479 | assign arlen = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? (4'b1 << (axi_rd_reg_size[axi_rdqueue_addrptr] - AXI_R_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:479:130: Operator SUB expects 32 bits on the LHS, but LHS's ARRAYSEL generates 3 bits.
: ... In instance mycpu_top.axi3x1
479 | assign arlen = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? (4'b1 << (axi_rd_reg_size[axi_rdqueue_addrptr] - AXI_R_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:479:89: Operator SHIFTL expects 8 bits on the LHS, but LHS's CONST '4'h1' generates 4 bits.
: ... In instance mycpu_top.axi3x1
479 | assign arlen = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? (4'b1 << (axi_rd_reg_size[axi_rdqueue_addrptr] - AXI_R_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:479:81: Operator COND expects 8 bits on the Conditional False, but Conditional False's CONST '3'h0' generates 3 bits.
: ... In instance mycpu_top.axi3x1
479 | assign arlen = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? (4'b1 << (axi_rd_reg_size[axi_rdqueue_addrptr] - AXI_R_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:480:63: Operator GT expects 32 bits on the LHS, but LHS's ARRAYSEL generates 3 bits.
: ... In instance mycpu_top.axi3x1
480 | assign arsize = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? AXI_R_BUS_SIZE : axi_rd_reg_size[axi_rdqueue_addrptr];
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:480:81: Operator COND expects 32 bits on the Conditional False, but Conditional False's ARRAYSEL generates 3 bits.
: ... In instance mycpu_top.axi3x1
480 | assign arsize = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? AXI_R_BUS_SIZE : axi_rd_reg_size[axi_rdqueue_addrptr];
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:480:21: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
: ... In instance mycpu_top.axi3x1
480 | assign arsize = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? AXI_R_BUS_SIZE : axi_rd_reg_size[axi_rdqueue_addrptr];
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:481:63: Operator GT expects 32 bits on the LHS, but LHS's ARRAYSEL generates 3 bits.
: ... In instance mycpu_top.axi3x1
481 | assign arburst = (axi_rd_reg_size[axi_rdqueue_addrptr] > AXI_R_BUS_SIZE) ? 2'b1 : 2'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:492:42: Operator GT expects 32 bits on the LHS, but LHS's VARREF 'axi_wr_reg_size' generates 3 bits.
: ... In instance mycpu_top.axi3x1
492 | assign awlen = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? (4'b1 << (axi_wr_reg_size - AXI_W_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:492:88: Operator SUB expects 32 bits on the LHS, but LHS's VARREF 'axi_wr_reg_size' generates 3 bits.
: ... In instance mycpu_top.axi3x1
492 | assign awlen = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? (4'b1 << (axi_wr_reg_size - AXI_W_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:492:68: Operator SHIFTL expects 8 bits on the LHS, but LHS's CONST '4'h1' generates 4 bits.
: ... In instance mycpu_top.axi3x1
492 | assign awlen = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? (4'b1 << (axi_wr_reg_size - AXI_W_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^~
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:492:60: Operator COND expects 8 bits on the Conditional False, but Conditional False's CONST '3'h0' generates 3 bits.
: ... In instance mycpu_top.axi3x1
492 | assign awlen = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? (4'b1 << (axi_wr_reg_size - AXI_W_BUS_SIZE)) >> 1'b1 : 3'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:493:42: Operator GT expects 32 bits on the LHS, but LHS's VARREF 'axi_wr_reg_size' generates 3 bits.
: ... In instance mycpu_top.axi3x1
493 | assign awsize = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? AXI_W_BUS_SIZE : axi_wr_reg_size;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:493:60: Operator COND expects 32 bits on the Conditional False, but Conditional False's VARREF 'axi_wr_reg_size' generates 3 bits.
: ... In instance mycpu_top.axi3x1
493 | assign awsize = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? AXI_W_BUS_SIZE : axi_wr_reg_size;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:493:21: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's COND generates 32 bits.
: ... In instance mycpu_top.axi3x1
493 | assign awsize = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? AXI_W_BUS_SIZE : axi_wr_reg_size;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:494:42: Operator GT expects 32 bits on the LHS, but LHS's VARREF 'axi_wr_reg_size' generates 3 bits.
: ... In instance mycpu_top.axi3x1
494 | assign awburst = (axi_wr_reg_size > AXI_W_BUS_SIZE) ? 2'b1 : 2'b0;
| ^
%Warning-WIDTH: verilog_modules/AXI_complex/AXI_complex_triport.v:501:21: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's SHIFTR generates 64 bits.
: ... In instance mycpu_top.axi3x1
501 | assign wdata = axi_wr_reg_data_in >> (AXI_W_BUS_WIDTH * axi_wrqueue_data);
| ^
%Error: Exiting due to 24 warning(s)
make: *** [Makefile:15: verilator] Error 1

Most errors related to AXI modules. Those errors need to be fixed so that the code can be debugged using verilator.

Environment:

• OS: Ubuntu 20.04
• Verilator version: Verilator 4.200 2021-03-12 rev v4.200-16-gf0d66453
• Command: verilator --cc --exe --top-module mycpu_top --threads 1 --assert --x-assign unique --output-split 20000 -O3 verilog/mycpu_top.v verilog_modules/AXI_complex/AXI_complex_triport.v