Issues
- 0
FU: CP0 unit test
#5 opened by ziyue-pan - 0
FU: WB unit test
#6 opened by ziyue-pan - 0
Interruption will not occur in delay slot, be aware and needs further consideration
#14 opened by ziyue-pan - 0
- 0
TODO: ASID's machine behavior in CP0
#17 opened by ziyue-pan - 0
- 1
CP0 Cause.IP(7,2) should be wires directly from input interrupts, not regs
#16 opened by ProjectDimlight - 0
- 0
Deal with debug_interface
#13 opened by ProjectDimlight - 0
Add support for time interrupt
#12 opened by ziyue-pan - 2
Put INT in FU stage, `flush` signal in WB
#11 opened by ziyue-pan - 1
- 1
CP0: exception after mtc0 WAW
#8 opened by ziyue-pan