Pinned Repositories
e203_hbirdv2
The Ultra-Low Power RISC-V Core
fpga-rocket-chip
Wrapper for Rocket-Chip on FPGAs
OpenMV_PCB
OpenMV PCB Project
riscv-v-spec
Working draft of the proposed RISC-V V vector extension
Smart-Internet-of-Thing-Alarm
基于STM32F103C8T_MCU的物联网智能闹钟，在V1.0测试版本当中，实现OLED屏幕显示和无线WiFi连接还有蓝牙通信，同时能够通过LM75芯片实现环境温度数据采集。
The-Automatic-Survey-and-Fire-Fighting-Robot
The Robot is based on the MCU STM32F103ZET6,which has realized some functions such as fire-fighting,attitude calculation and four-wheel drive.
The-Tetris
The Classic Game-the Tetris made by C language program with Console API and implementation of keyboard.
tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
XiangShan
Open-source high-performance RISC-V processor
Prussian516's Repositories
Prussian516/Smart-Internet-of-Thing-Alarm
基于STM32F103C8T_MCU的物联网智能闹钟，在V1.0测试版本当中，实现OLED屏幕显示和无线WiFi连接还有蓝牙通信，同时能够通过LM75芯片实现环境温度数据采集。
Prussian516/e203_hbirdv2
The Ultra-Low Power RISC-V Core
Prussian516/FPGAVerilogHDL
The Repository focused on developing the FPGA based on Verilog Hardware Device Language.
Prussian516/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
Prussian516/fpga-rocket-chip
Wrapper for Rocket-Chip on FPGAs
Prussian516/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
Prussian516/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Prussian516/XiangShan
Open-source high-performance RISC-V processor
Prussian516/ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
Prussian516/asio
Boost.org asio module
Prussian516/bnn-fpga
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
Prussian516/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Prussian516/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Prussian516/cppzmq
Header-only C++ binding for libzmq
Prussian516/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Prussian516/docs
OpenHarmony documentation | OpenHarmony开发者文档
Prussian516/finn
Dataflow compiler for QNN inference on FPGAs
Prussian516/finn-hlslib
Vivado HLS library for FINN
Prussian516/Image-processing-algorithm
paper implement
Prussian516/json
JSON for Modern C++
Prussian516/mmdeploy
OpenMMLab Model Deployment Framework
Prussian516/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Prussian516/picorv32_Xilinx
A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
Prussian516/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Prussian516/ppl.nn
A primitive library for neural network
Prussian516/rvv-intrinsic-doc
Prussian516/SEASKY_K210
K210 PCB YOLO
Prussian516/Verilog_FPGA_Vision
Prussian516/Vitis_HLS_Libraries
Vitis Libraries
Prussian516/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard